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EP1AGX Datasheet(PDF) 85 Page - Altera Corporation |
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EP1AGX Datasheet(HTML) 85 Page - Altera Corporation |
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85 / 234 page  Chapter 2: Arria GX Architecture 2–79 PLLs and Clock Networks © December 2009 Altera Corporation Arria GX Device Handbook, Volume 1 Table 2–21. Global and Regional Clock Connections from Bottom Clock Pins and Enhanced PLL Outputs Bottom Side Global and Regional Clock Network Connectivity Clock pins CLK4p vv v —— v —— — v ——— CLK5p vv v ——— v —— — v —— CLK6p v —— vv —— v ——— v — CLK7p v —— vv ——— v ——— v CLK4n — v ——— v —— — v ——— CLK5n — — v ——— v —— — v —— CLK6n — — — v ——— v ——— v — CLK7n — — — — v ——— v ——— v Drivers from internal logic GCLKDRV0 — v —————— ————— GCLKDRV1 — — v ————— ————— GCLKDRV2 — — — v ———— ————— GCLKDRV3 —— —— v ——— ————— RCLKDRV0 —— ——— v —— — v ——— RCLKDRV1 —— ———— v —— — v —— RCLKDRV2 —— ————— v ——— v — RCLKDRV3 —— —————— v ——— v RCLKDRV4 —— ——— v —— — v ——— RCLKDRV5 —— ———— v —— — v —— RCLKDRV6 —— ————— v ——— v — RCLKDRV7 —— —————— v ——— v Enhanced PLL 6 outputs c0 vv v —— v —— — v ——— c1 vv v ——— v —— — v —— c2 v —— vv —— v —— v c3 v —— vv ——— v ——— v c4 v — ——— v — v — v — v — c5 v — ———— v — v — v — v Enhanced PLL 12 outputs c0 — vv —— v —— — v ——— c1 — vv ——— v —— — v —— c2 — — — vv —— v ——— v — c3 — — — vv ——— v ——— v c4 —— ——— v — v — v — v — c5 —— ———— v — v — v — v |
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