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EP1AGX Datasheet(PDF) 57 Page - Altera Corporation |
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EP1AGX Datasheet(HTML) 57 Page - Altera Corporation |
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57 / 234 page  Chapter 2: Arria GX Architecture 2–51 TriMatrix Memory © December 2009 Altera Corporation Arria GX Device Handbook, Volume 1 M4K RAM Blocks The M4K RAM block includes support for true dual-port RAM. The M4K RAM block is used to implement buffers for a wide variety of applications such as storing processor code, implementing lookup schemes, and implementing larger memory applications. Each block contains 4,608 RAM bits (including parity bits). M4K RAM blocks can be configured in the following modes: ■ True dual-port RAM ■ Simple dual-port RAM ■ Single-port RAM ■ FIFO ■ ROM ■ Shift register When configured as RAM or ROM, you can use an initialization file to pre-load the memory contents. M4K RAM blocks allow for different clocks on their inputs and outputs. Either of the two clocks feeding the block can clock M4K RAM block registers (renwe, address, byte enable , datain, and output registers). Only the output register can be bypassed. The six labclk signals or local interconnects can drive the control signals for the A and B ports of the M4K RAM block. ALMs can also control the clock_a, clock_b , renwe_a, renwe_b, clr_a, clr_b, clocken_a, and clocken_b signals, as shown in Figure 2–44. Figure 2–43. M512 RAM Block LAB Row Interface dataout M4K RAM Block datain address 16 36 Direct link interconnect from adjacent LAB Direct link interconnect to adjacent LAB Direct link interconnect from adjacent LAB Direct link interconnect to adjacent LAB M4K RAM Block Local Interconnect Region C4 Interconnect R4 Interconnect LAB Row Clocks clocks byte enable control signals 6 |
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