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EP1AGX Datasheet(PDF) 52 Page - Altera Corporation |
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EP1AGX Datasheet(HTML) 52 Page - Altera Corporation |
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52 / 234 page  2–46 Chapter 2: Arria GX Architecture MultiTrack Interconnect Arria GX Device Handbook, Volume 1 © December 2009 Altera Corporation C4 interconnects span four LABs, M512, or M4K blocks up or down from a source LAB. Every LAB has its own set of C4 interconnects to drive either up or down. Figure 2–41 shows the C4 interconnect connections from a LAB in a column. C4 interconnects can drive and be driven by all types of architecture blocks, including DSP blocks, TriMatrix memory blocks, and column and row IOEs. For LAB interconnection, a primary LAB or its LAB neighbor can drive a given C4 interconnect. C4 interconnects can drive each other to extend their range as well as drive row interconnects for column-to-column connections. Figure 2–40. Shared Arithmetic Chain, Carry Chain and Register Chain Interconnects ALM 1 ALM 2 ALM 3 ALM 4 ALM 5 ALM 6 ALM 8 ALM 7 Carry Chain & Shared Arithmetic Chain Routing to Adjacent ALM Local Interconnect Register Chain Routing to Adjacent ALM's Register Input Local Interconnect Routing Among ALMs in the LAB |
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