10

FN9220.0

September 27, 2005

If EN2 is brought high, and EN1 goes high before the VO2

output stablizes, the ISL9012 delays the VO1 turn-on until

the VO2 output reaches its target level.

If both EN1 and EN2 are high, the VO1 output has priority,

and is always powered up first.

During operation, whenever the VIN voltage drops below

about 1.8V, the ISL9012 immediately disables both LDO

outputs. When VIN rises back above 2.1V, the device re-

initiates its start-up sequence and LDO operation will

resume automatically.

Reference Generation

The reference generation circuitry includes a trimmed

bandgap, a trimmed voltage reference divider, a trimmed

current reference generator, and an RC noise filter. The filter

includes the external capacitor connected to the CBYP pin.

A 0.01

µF capacitor connected CBYP implements a 100Hz

lowpass filter, and is recommended for most high

performance applications. For the lowest noise application, a

0.1

µF or greater CBYP capacitor should be used. This filters

the reference noise to below the 10Hz – 1kHz frequency

band, which is crucial in many noise-sensitive applications.

The bandgap generates a zero temperature coefficient (TC)

voltage for the reference divider. The reference divider

provides the regulation reference, POR detection thresholds,

and other voltage references required for current generation

and over-temperature detection.

The current generator outputs references required for

adaptive biasing as well as references for LDO output

current limit and thermal shutdown determination.

LDO Regulation and Programmable Output Divider

The LDO Regulator is implemented with a high-gain

operational amplifier driving a PMOS pass transistor. The

design of the ISL9012 provides a regulator that has low

quiescent current, fast transient response, and overall

stability across all operating and load current conditions.

LDO stability is guaranteed for a 1

µF to 10µF output

capacitor that has a tolerance better than 20% and ESR less

µF

capacitor. Unless limited by the application, use of an output

capacitor value above 4.7

µF is not recommended as LDO

performance improvement is minimal.

Soft-start circuitry integrated into each LDO limits the initial

ramp-up rate to about 30

µs/V to minimize current surge. The

ISL9012 provides short-circuit protection by limiting the

output current to about 475mA.

Each LDO uses an independently trimmed 1V reference. An

internal resistor divider drops the LDO output voltage down

to 1V. This is compared to the 1V reference for regulation.

The resistor division ratio is programmed in the factory to

one of the following output voltages: 1.5V, 1.8V, 1.85, 2.5V,

2.6, 2.7, 2.8V, 2.85V, 2.9, 3.0, and 3.3V.

Power On Reset Generation

LDO-2 has a Power-on Reset signal generation circuit which

outputs to the POR pin. The POR signal is generated as

follows:

A POR comparator continuously monitors the voltage of the

LDO-2 output. The LDO enters a power-good state when the

output voltage is above 94% of the expected output voltage

for a period exceeding the LDO PGOOD entry delay time. In

the power-good state, the open-drain POR output is in a

high-impedance state. An external resistor can be added

between the POR output and either LDO output or the input

voltage, VIN.

The power-good state is exited when the LDO-2 output falls

below 90% of the expected output voltage for a period longer

than the PGOOD exit delay time. While power-good is false,

the ISL9012 pulls the respective POR pin low.

The PGOOD entry and exit delays are determined by the

value of the external capacitor connected to the CPOR pin.

For a 0.01

µF capacitor, the entry and exit delays are 200ms

and 25

µs respectively. Larger or smaller capacitor values will

yield proportionately longer or shorter delay times. The POR

exit delay should never be allowed to be less than 10

µs to

ensure sufficient immunity against transient induced false

POR triggering.

Overheat Detection

The bandgap outputs a proportional-to-temperature current

that is indicative of the temperature of the silicon. This

current is compared with references to determine if the

device is in danger of damage due to overheating. When the

die temperature reaches about 145°C, one or both of the

LDO’s momentarily shut down until the die cools sufficiently.

In the overheat condition, only the LDO sourcing more than

50mA will be shut off. This does not affect the operation of

the other LDO. If both LDOs source more than 50mA and an

overheat condition occurs, both LDO outputs are disabled.

Once the die temperature falls back below about 110°C, the

disabled LDO(s) are re-enabled and soft-start automatically

takes place.

ISL9012