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ISL6520B Datasheet(PDF) 5 Page - Intersil Corporation |
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ISL6520B Datasheet(HTML) 5 Page - Intersil Corporation |
5 / 10 page 5 FN9083.2 January 20, 2005 rail, which supplies the bias voltage to the ISL6520B. If there is nowhere for this current to go, such as to other distributed loads on the VCC rail, through a voltage limiting protection device, or other methods, the capacitance on the VCC bus will absorb the current. This situation will allow voltage level of the VCC rail to increase. If the voltage level of the rail is boosted to a level that exceeds the maximum voltage rating of the ISL6520B, then the IC will experience an irreversible failure and the converter will no longer be operational. Ensuring that there is a path for the current to follow other than the capacitance on the rail will prevent this failure mode. Application Guidelines Layout Considerations As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. These interconnecting impedances should be minimized by using wide, short printed circuit traces. The critical components should be located as close together as possible, using ground plane construction or single point grounding. Figure 2 shows the critical power components of the converter. To minimize the voltage overshoot, the interconnecting wires indicated by heavy lines should be part of a ground or power plane in a printed circuit board. The components shown in Figure 2 should be located as close together as possible. Please note that the capacitors CIN and CO may each represent numerous physical capacitors. Locate the ISL6520B within 3 inches of the MOSFETs, Q1 and Q2. The circuit traces for the MOSFETs’ gate and source connections from the ISL6520B must be sized to handle up to 1A peak current. Figure 3 shows the circuit traces that require additional layout consideration. Use single point and ground plane construction for the circuits shown. Minimize any leakage current paths on the COMP/SD pin and locate the resistor, ROSCET close to the COMP/SD pin because the internal current source is only 20 µA. Provide local VCC decoupling between VCC and GND pins. Locate the capacitor, CBOOT as close as practical to the BOOT and PHASE pins. All components used for feedback compensation should be located as close to the IC a practical. Feedback Compensation Figure 4 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (VOUT) is regulated to the Reference voltage level. The error amplifier (Error Amp) output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (LO and CO). The modulator transfer function is the small-signal transfer function of VOUT/VE/A. This function is dominated by a DC Gain and the output filter (LO and CO), with a double pole LO CO LGATE UGATE PHASE Q1 Q2 VIN VOUT RETURN ISL6520B CIN FIGURE 2. PRINTED CIRCUIT BOARD POWER AND GROUND PLANES OR ISLANDS FIGURE 3. PRINTED CIRCUIT BOARD SMALL SIGNAL LAYOUT GUIDELINES +5V ISL6520B GND VCC BOOT D1 LO CO VOUT Q1 Q2 PHASE +VIN CBOOT CVCC FIGURE 4. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN VOUT REFERENCE LO CO ESR VIN ∆VOSC ERROR AMP PWM DRIVER (PARASITIC) ZFB + - REFERENCE R1 R3 R2 C3 C2 C1 COMP/SD VOUT FB ZFB ISL6520B ZIN COMPARATOR DRIVER DETAILED COMPENSATION COMPONENTS PHASE VE/A + - + - ZIN OSC ISL6520B |
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