ISL8723 datasheet(4/14 Pages) INTERSIL

Part #	ISL8723

Description	Power Sequencing Controllers

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Manufacturer	INTERSIL [Intersil Corporation]

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4

FN6413.0

December 21, 2006

Absolute Maximum Ratings

Thermal Information

VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V

GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+6V

UVLO, ENABLE, ENABLE#, SYSRST# . . . . . . -0.3V to VDD +0.3V

RESET#, DLY_ON, DLYOFF . . . . . . . . . . . . . . . -0.3V to VDD +0.3V

Operating Conditions

VDD Supply Voltage Range . . . . . . . . . . . . . . . . . . . . +2.5V to +5.0V

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Thermal Resistance (Typical, Notes 1, 2)

θJA (°C/W) θJC (°C/W)

4 x 4 QFN Package . . . . . . . . . . . . . . .

48

9

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . +125°C

Maximum Storage Temperature Range . . . . . . . . . . -65°C to +150°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1.

θ

JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

Tech Brief TB379.

2. For

θJC, the “case temp” location is the center of the exposed metal pad on the package underside.

3. All voltages are relative to GND, unless otherwise specified.

Electrical Specifications

VDD = 3.3V to +5V, TA = TJ = -40°C to +85°C, Unless Otherwise Specified.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

UVLO

Undervoltage Lockout Falling Threshold

VUVLOvth

TA = TJ = +25°C

619

631

647

mV

Undervoltage Lockout Falling Threshold

VUVLOvth

604

631

656

mV

Undervoltage Lockout Hysteresis

VUVLOhys

-9

-

mV

Undervoltage Lockout Threshold Range

RUVLOvth

Max VUVLOvth- Min VUVLOvth

-6

18

mV

Undervoltage Lockout Delay

TUVLOdel

ENABLE satisfied

-

10

-

ms

Transient Filter Duration

tFIL

VDD, UVLO, ENABLE glitch filter

-

7

-

μs

DELAY ON/OFF

Delay Charging Current

DLY_ichg

VDLY = 0V

0.9

1

1.115

μA

Delay Charging Current Range

DLY_ichg_r

DLY_ichg(max) - DLY_ichg(min)

-

0.01

0.05

μA

Delay Threshold Voltage

DLY_Vth

1.21

1.273

1.32

V

ENABLE/ENABLE#, RESET# AND SYSRST# I/O

ENABLE Threshold

VENh

Measured at VDD = 5V

-

1.28

1.35

V

ENABLE# Threshold

VENh

-0.5 VDD

-V

ENABLE/ENABLE# Hysteresis

VENh -VENl

Measured at VDD = 5V

-

0.1

0.2

V

ENABLE/ENABLE# Lockout Delay

TdelEN_LO

UVLO satisfied, EN to DLY_ON

-

10

-

ms

ENABLE/ENABLE# Input Capacitance

Cin_en

-

5

-

pF

RESET# Pull-up Voltage

Vpu_rst

-

VDD

-V

RESET# Pull-Down Current

IRSTpd5

VDD = 5V, RST = 0.1V

-

13

-

mA

RESET# Delay after GATE High

TRSTdel

GATE = VDD+5V

-

160

-

ms

RESET# Output Low

VRSTl

Measured at VDD = 5V, 1mA

sourcing current

--

0.1

V

RESET Output Capacitance

Cout_rst

-

10

-

pF

SYSRST# Pull-up Voltage

Vpu_srst

-

VDD-0.5V

-

V

SYSRST# Pull-up Current

Ipu_srst

VDD = 3.3V, SYSRST# = 0.5V

-

12

-

μA

SYSRST# Pull Down Current

Ipu_5

VDD = 5V

-

2.7

-

μA

SYSRST# Low Output Voltage

Vol_srst

VDD = 5V, IOUT = 100μA-

0.1

V

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