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ISL6527IRZ Datasheet(PDF) 10 Page - Intersil Corporation |
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ISL6527IRZ Datasheet(HTML) 10 Page - Intersil Corporation |
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10 / 16 page  10 FN9056.10 November 18, 2008 The modulator transfer function is the small-signal transfer function of VOUT/VE/A. This function is dominated by a DC Gain and the output filter (LO and CO), with a double pole break frequency at FLC and a zero at FESR. The DC Gain of the modulator is simply the input voltage (VIN) divided by the peak-to-peak oscillator voltage ΔV OSC . Modulator Break Frequency Equations The compensation network consists of the error amplifier (internal to the ISL6527, ISL6527A) and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180°. Equations 7 through 10 relate the compensation network’s poles, zeros and gain to the components (R1, R2, R3, C1, C2, and C3) in Figure 5. Use these guidelines for locating the poles and zeros of the compensation network: 1. Pick gain (R2/R1) for desired converter bandwidth. 2. Place first zero below filter’s double pole (~75% FLC). 3. Place second zero at filter’s double-pole. 4. Place first pole at the ESR zero. 5. Place second pole at half the switching frequency. 6. Check gain against error amplifier’s open-loop gain. 7. Estimate phase margin; repeat if necessary. Compensation Break Frequency Equations Figure 6 shows an asymptotic plot of the DC/DC converter’s gain vs frequency. The actual modulator gain has a high gain peak due to the high Q factor of the output filter and is not shown in Figure 6. Using the above guidelines should give a compensation gain similar to the curve plotted. The open loop VOUT ISLAND ON POWER PLANE LAYER ISLAND ON CIRCUIT PLANE LAYER LOUT COUT CIN +3.3V VIN KEY COMP ISL6527, ISL6527A UGATE R4 R2 CBP FB GND CPVOUT FIGURE 4. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS R1 BOOT C2 VIA CONNECTION TO GROUND PLANE Q1 CBOOT PHASE D1 R3 C3 C1 Q2 LGATE PHASE VCC CVCC F LC 1 2 π x L O x CO ------------------------------------------ = (EQ. 5) F ESR 1 2 π x ESR x C O ------------------------------------------- = (EQ. 6) FIGURE 5. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN VOUT REFERENCE LO CO ESR VIN DVOSC ERROR AMP PWM DRIVER (PARASITIC) ZFB + - REFERENCE R1 R3 R2 C3 C1 C2 COMP VOUT FB ZFB ISL6527 ZIN COMPARATOR DRIVER DETAILED COMPENSATION COMPONENTS PHASE VE/A + - + - ZIN OSC F Z1 1 2 π R 2 × C 2 × ---------------------------------- = (EQ. 7) F P1 1 2 π x R 2 x C 1 x C2 C 1 C 2 + ---------------------- ⎝⎠ ⎜⎟ ⎛⎞ --------------------------------------------------------- = (EQ. 8) F Z2 1 2 π x R 1 R 3 + () x C 3 ------------------------------------------------------- = (EQ. 9) F P2 1 2 π x R 3 x C3 ------------------------------------ = (EQ. 10) ISL6527, ISL6527A |
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