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FN9257.0

February 13, 2006

ISL8104

OCSET (Pin 2/15)

The current limit is programmed by connecting this pin with a

resistor and capacitor to the drain of the high side MOSEFT.

resistor which is then compared with the voltage developed

across the high side MOSFET. A blanking period of 120ns is

provided for noise immunity.

SS (Pin 3/1)

Connect a capacitor from this pin to ground. This capacitor,

along with an internal 30

µA current source, sets the soft-start

interval of the converter.

COMP (Pin 4/2) and FB (Pin 5/3)

COMP and FB are the available external pins of the error

amplifier. The FB pin is the inverting input of the error ampli-

fier and the COMP pin is the error amplifier output. These

pins are used to compensate the voltage-control feedback

loop of the converter.

EN (Pin 6/4)

This pin is a TTL compatible input. Pull this pin below 0.8V to

disable the converter. In shutdown the soft-start pin is

discharged and the UGATE and LGATE pins are held low.

GND (Pin 7/6)

Signal ground for the IC. All voltage levels are measured

with respect to this pin.

PHASE (Pin 8/7)

This pin connects to the source of the high side MOSFET

and the drain of the low side MOSFET. This pin represents

the return path for the high side gate driver. During normal

switching, this pin is used for high side current sensing.

UGATE (Pin 9/8)

Connect UGATE to the upper MOSFET gate. This pin

provides the gate drive for the upper MOSFET.

BOOT (Pin 10/9)

This pin provides bias to the upper MOSFET driver. A

bootstrap circuit may be used to create a BOOT voltage

suitable to drive a standard N-Channel MOSFET.

PGND (Pin 11/10)

This is the power ground connection. Tie the lower MOSFET

source and board ground to this pin.

LGATE (Pin 12/11)

Connect LGATE to the lower MOSFET gate. This pin

provides the gate drive for the lower MOSFET.

PVCC (Pin 13/12)

Provide an 8V to 14V bias supply for the lower gate drive to

this pin. This pin should be bypassed with a capacitor to

PGND.

VCC (Pin 14/13)

Provide an 8V to 14V bias supply for the chip to this pin. The

pin should be bypassed with a capacitor to GND.

REFIN (QFN ONLY Pin 5)

Upon enable if REFIN is less than 2.2V, the external

reference pin is used as the control reference instead of the

provided for disabling this functionality.

SSDONE (QFN ONLY Pin 16)

Provides an open drain signal at the end of soft-start.

Functional Description

Initialization

The ISL8104 automatically initializes upon receipt of power.

Special sequencing of the input supplies is not necessary.

The Power-On Reset (POR) function continually monitors

the bias voltage at the VCC pin and the driver input on the

PVCC pin. When the voltages at VCC and PVCC exceed

their rising POR thresholds, a 30

µA current source driving

the SS pin is enabled. Upon the SS pin exceeding 1V, the

ISL8104 begins ramping the non-inverting input of the error

amplifier from GND to the System Reference. During

initialization the MOSFET drivers pull UGATE to PHASE and

LGATE to PGND.

Soft-Start

During soft-start, an internal 30

µA current source charges the

ISL8104 is utilizing the internal reference, then as the SS pin’s

voltage ramps from 1V to 3V, the soft-start function scales the

reference input (positive terminal of error amp) from GND to

VREF (0.597V nominal). If the ISL8104 is utilizing an

externally supplied reference, when the voltage on the SS pin

reaches 1V, the internal reference input (into of the error amp)

ramps from GND to the externally supplied reference at the

same rate as the voltage on the SS pin. Figure 3 shows a

FIGURE 3. TYPICAL SOFT-START INTERVAL