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ISL6532ACR Datasheet(PDF) 15 Page  Intersil Corporation 

ISL6532ACR Datasheet(HTML) 15 Page  Intersil Corporation 
15 / 17 page 15 FN9099.5 May 5, 2008 Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values reduce the converter’s response time to a load transient. One of the parameters limiting the converter’s response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the ISL6532A will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. The following equations give the approximate response time interval for application and removal of a transient load: where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. The worst case response time can be either at the application or removal of load. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. Input Capacitor Selection  PWM Buck Converter Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time the upper MOSFET turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of upper MOSFET and the source of lower MOSFET. The important parameters for the bulk input capacitance are the voltage rating and the RMS current rating. For reliable operation, select bulk capacitors with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. Their voltage rating should be at least 1.25 times greater than the maximum input voltage, while a voltage rating of 1.5 times is a conservative guideline. For most cases, the RMS current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the DC load current. The maximum RMS current required by the regulator may be closely approximated through Equation 11: For a through hole design, several electrolytic capacitors may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surgecurrent at powerup. Some capacitor series available from reputable manufacturers are surge current tested. MOSFET Selection  PWM Buck Converter The ISL6532A requires 2 NChannel power MOSFETs for switching power and a third MOSFET to block backfeed from VDDQ to the Input in S3 Mode. These should be selected based upon rDS(ON), gate supply requirements, and thermal management requirements. In highcurrent applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components; conduction loss and switching loss. The conduction losses are the largest component of power dissipation for both the upper and the lower MOSFETs. These losses are distributed between the two MOSFETs according to duty factor. The switching losses seen when sourcing current will be different from the switching losses seen when sinking current. When sourcing current, the upper MOSFET realizes most of the switching losses. The lower switch realizes most of the switching losses when the converter is sinking current (see the following equations). These equations assume linear voltagecurrent transitions and do not adequately model power loss due the reverse recovery of the upper and lower MOSFET’s body diode. The gatecharge losses are dissipated in part by the ISL6532A and do not significantly heat the MOSFETs. However, large gatecharge increases the switching interval, tSW which increases the MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermalresistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow. tRISE = L x ITRAN VIN  VOUT tFALL = L x ITRAN VOUT (EQ. 10) I RMS MAX V OUT V IN  I OUT MAX 2 1 12  V IN  VOUT Lf s ×  V OUT V IN  × ⎝⎠ ⎛⎞ 2 × + ⎝⎠ ⎛⎞ × = (EQ. 11) PLOWER = Io 2 x r DS(ON) x (1  D) Where: D is the duty cycle = VOUT / VIN, tSW is the combined switch ON and OFF time, and fs is the switching frequency. Approximate Losses while Sourcing current Approximate Losses while Sinking current P LOWER Io 2 r DS ON () × 1  D () × 1 2  Io ⋅ V IN × t SW f s × × + = P UPPER Io 2 r DS ON () × D × 1 2  Io ⋅ V IN × t SW f s × × + = PUPPER = Io 2 x r DS(ON) x D (EQ. 12) ISL6532A 
