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ISL6532ACR Datasheet(PDF) 14 Page - Intersil Corporation

Part No. ISL6532ACR
Description  ACPI Regulator/Controller for Dual Channel DDR Memory Systems
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL6532ACR Datasheet(HTML) 14 Page - Intersil Corporation

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14
FN9099.5
May 5, 2008
To properly compensate the LDO system, a 100k
Ω 1%
resistor and a 680pF X5R ceramic capacitor, represented as
R10 and C25 in Figure 7, are used. This compensation will
insure a stable system with any MOSFET given the following
conditions:
Maximum bandwidth will be realized at full load while
minimum bandwidth will be realized at no load. Bandwidth at
no load will be maximized as
τ becomes closer to 10μs.
Output Voltage Selection
The output voltage of the VDDQ PWM converter can be
programmed to any level between VIN and the internal
reference, 0.8V. An external resistor divider is used to scale
the output voltage relative to the reference voltage and feed
it back to the inverting input of the error amplifier, see
Figure 5. However, since the value of R1 affects the values of
the rest of the compensation components, it is advisable to
keep its value less than 5k
Ω. Depending on the value chosen
for R1, R4 can be calculated based on the Equation 7:
If the output voltage desired is 0.8V, simply route VDDQ back
to the FB pin through R1, but do not populate R4.
The output voltage for the internal VTT linear regulator is set
internal to the ISL6532A to track the VDDQ voltage by 50%.
There is no need for external programming resistors.
As with the VDDQ PWM regulator, the AGP linear regulator
output voltage is set by means of an external resistor divider
as shown in Figure 7. For stability concerns described
earlier, the recommended value of the feedback resistor, R8,
is 249
Ω. The voltage programming resistor, R9 can be
calculated based on the Equation 8:
Component Selection Guidelines
Output Capacitor Selection - PWM Buck Converter
An output capacitor is required to filter the inductor current
and supply the load transient current. The filtering
requirements are a function of the switching frequency and
the ripple current. The load transient requirements are a
function of the slew rate (di/dt) and the magnitude of the
transient load current. These requirements are generally met
with a mix of capacitors and careful layout.
DDR memory systems are capable of producing transient
load rates above 1A/ns. High frequency capacitors initially
supply the transient and slow the current load rate seen by
the bulk capacitors. The bulk filter capacitor values are
generally determined by the ESR (Effective Series
Resistance) and voltage rating requirements rather than
actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient.
An aluminum electrolytic capacitor’s ESR value is related to
the case size with lower ESR available in larger case sizes.
However, the Equivalent Series Inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient
loading. Unfortunately, ESL is not a specified parameter.
Work with your capacitor supplier and measure the
capacitor’s impedance with frequency to select a suitable
component. In most cases, multiple electrolytic capacitors of
small case size perform better than a single large case
capacitor.
Output Capacitor Selection - LDO Regulators
The output capacitors used in LDO regulators are used to
provide dynamic load current. The amount of capacitance
and type of capacitor should be chosen with this criteria in
mind.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by the following equations:
DRIVE2
FB2
ISL6532A
VAGP
VDDQ
FIGURE 7. COMPENSATION AND OUTPUT VOLTAGE
SELECTION OF THE LINEAR
650
Ω
R9
R10
C25
+
-
0.8V
+
OUTPUT
IMPEDANCE
R8
REFERENCE
ESR
COUT
RLOAD
V
AGP
0.8
1
R
8
R
9
-------
+
⎝⎠
⎜⎟
⎛⎞
×
=
τ
C
OUT ESR
10
μs
>
=
R
FB
R
8
249
Ω
==
(EQ. 6)
R
4
R1
0.8V
×
V
DDQ - 0.8V
------------------------------------
=
(EQ. 7)
R
9
R
8
0.8V
×
V
AGP - 0.8 V
-----------------------------------
=
(EQ. 8)
ΔI=
VIN - VOUT
Fs x L
VOUT
VIN
ΔV
OUT = ΔI x ESR
x
(EQ. 9)
ISL6532A


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