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ISL6532ACR Datasheet(PDF) 13 Page - Intersil Corporation

Part No. ISL6532ACR
Description  ACPI Regulator/Controller for Dual Channel DDR Memory Systems
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL6532ACR Datasheet(HTML) 13 Page - Intersil Corporation

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FN9099.5
May 5, 2008
The modulator transfer function is the small-signal transfer
function of VOUT/VE/A. This function is dominated by a DC
Gain and the output filter (LO and CO), with a double pole
break frequency at FLC and a zero at FESR. The DC Gain of
the modulator is simply the input voltage (VIN) divided by the
peak-to-peak oscillator voltage
ΔV
OSC .
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL6532A) and the impedance networks ZIN
and ZFB. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f0dB) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f0dB and
180°. The following equations relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 5. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth.
2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC).
3. Place 2ND Zero at Filter’s Double Pole.
4. Place 1ST Pole at the ESR Zero.
5. Place 2ND Pole at Half the Switching Frequency.
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
Compensation Break Frequency Equations
Figure 6 shows an asymptotic plot of the DC-DC converter’s
gain vs frequency. The actual Modulator Gain has a high
gain peak due to the high Q factor of the output filter and is
not shown in Figure 6. Using the above guidelines should
give a Compensation Gain similar to the curve plotted. The
open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at fP2 with the
capabilities of the error amplifier. The Closed Loop Gain is
constructed on the graph of Figure 6 by adding the
Modulator Gain (in dB) to the Compensation Gain (in dB).
This is equivalent to multiplying the modulator transfer
function to the compensation transfer function and plotting
the gain.
The compensation gain uses external impedance networks
ZFB and ZIN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45 °.
Include worst case component variations when determining
phase margin.
Feedback Compensation - AGP LDO Controller
Figure 7 shows the AGP LDO power and control stage. This
LDO, which uses a MOSFET as the linear pass element,
requires feedback compensation to insure stability of the
system. The LDO requires compensation because of the
output impedance of the error amplifier.
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
VDDQ
REFERENCE
LO
CO
ESR
VIN
ΔVOSC
ERROR
AMP
PWM
DRIVER
(PARASITIC)
ZFB
+
-
REFERENCE
R1
R3
R2
C3
C1
C2
COMP
VDDQ
FB
ZFB
ISL6532A
ZIN
COMPARATOR
DRIVER
DETAILED COMPENSATION COMPONENTS
PHASE
VE/A
+
-
+
-
ZIN
OSC
R4
V
DDQ
0.8
1
R
1
R
4
-------
+
⎝⎠
⎜⎟
⎛⎞
×
=
F
LC
1
2
π x L
O
x C
O
-------------------------------------------
=
F
ESR
1
2
π x ESR x C
O
--------------------------------------------
=
(EQ. 4)
f
Z1
1
2
π x R
2 x C2
------------------------------------
=
f
Z2
1
2
π x R
1
R
3
+
() x C
3
-------------------------------------------------------
=
f
P1
1
2
π x R
2 x
C
1 x C2
C
1
C
2
+
----------------------
⎝⎠
⎜⎟
⎛⎞
---------------------------------------------------------
=
f
P2
1
2
π x R
3 x C3
------------------------------------
=
(EQ. 5)
100
80
60
40
20
0
-20
-40
-60
fP1
fZ2
10M
1M
100k
10k
1k
100
10
OPEN LOOP
ERROR AMP GAIN
fZ1
fP2
20LOG
fLC
fESR
COMPENSATION
FREQUENCY (Hz)
GAIN
20LOG
(VIN/ΔVOSC)
MODULATOR
GAIN
(R2/R1)
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
CLOSED LOOP
GAIN
ISL6532A


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