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ISL6532ACR Datasheet(PDF) 10 Page - Intersil Corporation |
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ISL6532ACR Datasheet(HTML) 10 Page - Intersil Corporation |
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10 / 17 page 
10 FN9099.5 May 5, 2008 and the VDDQ switching regulator will be disabled. NCH is pulled low to disable the backfeed blocking MOSFET. PGOOD will also transition LOW. When VTT is disabled, the internal reference for the VTT regulator is internally shorted to the VTT rail. This allows the VTT rail to float. When floating, the voltage on the VTT rail will depend on the leakage characteristics of the memory and MCH I/O pins. It is important to note that the VTT rail may not bleed down to 0V. The VDDQ rail will be supported in the S3 state through the standby VDDQ LDO. When S3 transitions LOW, the Standby regulator is immediately enabled. The switching regulator is disabled synchronous to the switching waveform. The shut off time will range between 4µs and 8µs. The standby LDO is capable of supporting up to 650mA of load with P5VSBY tied to the 5V Standby Rail. The standby LDO may receive input from either the 3.3V Standby rail or the 5V Standby rail through the P5VSBY pin. It is recommended that the 5V Standby rail be used as the current delivery capability of the LDO is greater. SLEEP TO ACTIVE (S3 TO S0 TRANSITION) When SLP_S3 transitions from LOW to HIGH with SLP_S5 held HIGH and after the 12V rail exceeds POR, the ISL6532A will enable the VDDQ switching regulator, disable the VDDQ standby regulator, enable the VTT LDO and force the NCH pin to a high impedance state turning on the blocking MOSFET. The AGP LDO goes through a 2048 clock cycle soft-start. The internal short between the VTT reference and the VTT rail is released. Upon release of the short, the capacitor on VREF_IN is then charged up through the internal resistor divider network. The VTT output will follow this capacitor charge up, and acting as the S3 to S0 transition soft-start for the VTT rail. The PGOOD comparator is enabled only after 2048 clock cycles, or typically 8.2ms, have passed following the S3 transition to a HIGH state. Figure 2 illustrates a typical state transition from S3 to S0. It should be noted that the soft-start profile of the VTT LDO output will vary according to the value of the capacitor on the VREF_IN pin. ACTIVE TO SHUTDOWN (S0 TO S5 TRANSITION) When the system transitions from active (S0) state to shutdown (S4/S5) state, the ISL6532A IC disables all regulators and forces the PGOOD pin and the NCH pin LOW. VDDQ Overcurrent Protection (S0 State) The overcurrent function protects the switching converter from a shorted output by using the upper MOSFET ON- resistance, rDS(ON), to monitor the current. This method enhances the converter’s efficiency and reduces cost by eliminating a current sensing resistor. The overcurrent function cycles the soft-start function in a hiccup mode to provide fault protection. A resistor (ROCSET) programs the overcurrent trip level (see Typical Application Diagrams on page 4 and page 5). An internal 20 μA (typical) current sink develops a voltage across ROCSET that is referenced to the converter input voltage. When the voltage across the upper MOSFET (also referenced to the converter input voltage) exceeds the voltage across ROCSET, the over- current function initiates a soft-start sequence. The initiation of soft-start will affect all regulators. The VTT regulator is directly affected as it receives it’s reference from VDDQ. The AGP LDO will also be soft-started, and as such, the AGP LDO voltage will be disabled while the VDDQ regulator is disabled. Figure 3 illustrates the protection feature responding to an overcurrent event. At time T0, an overcurrent condition is sensed across the upper MOSFET. As a result, the regulator is quickly shutdown and the internal soft-start function begins producing soft-start ramps. The delay interval seen by the output is equivalent to three soft-start cycles. The fourth FIGURE 1. TYPICAL COLD START VTT VDDQ 12VATX 2V/DIV 5VSBY S3 S5 1V/DIV 500mV/DIV 500mV/DIV VAGP 500mV/DIV 12V POR SOFT-START INITIATES SOFT-START ENDS PGOOD COMPARATOR ENABLED 2048 CLOCK CYCLES 2048 CLOCK CYCLES PGOOD 5V/DIV FIGURE 2. TYPICAL S3 to S0 STATE TRANSITION VTT VDDQ 12VATX 2V/DIV S3 S5 500mV/DIV 500mV/DIV PGOOD 5V/DIV VAGP 500mV/DIV VTT_FLOAT 12V POR PGOOD COMPARATOR ENABLED 2048 CLOCK CYCLES ISL6532A |
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