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ISL6532ACR Datasheet(PDF) 8 Page - Intersil Corporation

Part No. ISL6532ACR
Description  ACPI Regulator/Controller for Dual Channel DDR Memory Systems
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL6532ACR Datasheet(HTML) 8 Page - Intersil Corporation

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8
FN9099.5
May 5, 2008
Functional Pin Description
5VSBY (Pin 2)
5VSBY is the bias supply of the ISL6532A. It is typically
connected to the 5V standby rail of an ATX power supply.
During S4/S5 sleep states the ISL6532A enters a reduced
power mode and draws less than 1mA (ICC_S5) from the
5VSBY supply. The supply to 5VSBY should be locally
bypassed using a 0.1
μF capacitor.
P12V (Pin 25)
P12V provides the gate drive to the switching MOSFETs of
the PWM power stage. The VTT regulation circuit and the
Linear Driver are also powered by P12V. P12V is not
required except during S0/S1/S2 operation. P12V is typically
connected to the +12V rail of an ATX power supply.
5VSBY (Pin 11)
This pin provides the VDDQ output power during S3 sleep
state. The regulator is capable of providing standby VDDQ
power from either the 5VSBY or 3.3VSBY rail. It is
recommended that the 5VSBY rail be used as the output
current handling capability of the standby LDO is higher than
with the 3.3VSBY rail.
GND, GNDA, GNDP, GNDQ (Pins 1, 3, 4, 17, 29)
The GND terminals of the ISL6532A provide the return path
for the VTT LDO, standby LDO and switching MOSFET gate
drivers. High ground currents are conducted directly through
the exposed paddle of the QFN package which must be
electrically connected to the ground plane through a path as
low in inductance as possible. GNDA is the Analog ground
pin, GNDQ is the return for the VTT regulator and GNDP is
the return for the upper and lower gate drives.
UGATE (Pin 26)
UGATE drives the upper (control) FET of the VDDQ
synchronous buck switching regulator. UGATE is driven
between GND and P12V.
LGATE (Pin 27)
LGATE drives the lower (synchronous) FET of the VDDQ
synchronous buck switching regulator. LGATE is driven
between GND and P12V.
FB (Pin 15) and COMP (Pin 16)
The VDDQ switching regulator employs a single voltage
control loop. FB is the negative input to the voltage loop error
amplifier. The positive input of the error amplifier is
connected to a precision 0.8V reference and the output of
the error amplifier is connected to the COMP pin. The VDDQ
output voltage is set by an external resistor divider
connected to FB. With a properly selected divider, VDDQ can
be set to any voltage between the power rail (reduced by
converter losses) and the 0.8V reference. Loop
compensation is achieved by connecting an AC network
across COMP and FB.
The FB pin is also monitored for under and overvoltage
events.
PHASE (Pin 20)
Connect this pin to the upper MOSFET’s source. This pin is
used to monitor the voltage drop across the upper MOSFET
for overcurrent protection.
OCSET (Pin 12)
Connect a resistor (ROCSET) from this pin to the drain of the
upper MOSFET, ROCSET, an internal 20μA current source
(IOCSET), and the upper MOSFET ON-resistance (rDS(ON)).
Set the converter overcurrent (OC) trip point according to
Equation 1:
An overcurrent trip cycles the soft-start function.
VDDQ (Pins 7, 8, 9)
The VDDQ pins should be connected externally together to
the regulated VDDQ output. During S0/S1 states, the VDDQ
pins serve as inputs to the VTT regulator and to the VTT
Reference precision divider. During S3 state, the VDDQ pins
serve as an output from the integrated standby LDO.
VTT (Pins 5, 6)
The VTT pins should be connected externally together.
During S0/S1 states, the VTT pins serve as the outputs of
the VTT linear regulator. During S3 state, the VTT regulator is
disabled.
VTTSNS (Pin 10)
VTTSNS is used as the feedback for control of the VTT linear
regulator. Connect this pin to the VTT output at the physical
point of desired regulation.
VREF_OUT (Pin 13)
VREF_OUT is a buffered version of VTT and also acts as the
reference voltage for the VTT linear regulator. It is
recommended that a minimum capacitance of 0.1
μF is
connected between VDDQ and VREF_OUT and also
between VREF_OUT and ground for proper operation.
VREF_IN (Pin 14)
A capacitor, CSS, connected between VREF_IN and ground
is required. This capacitor and the parallel combination of
the Upper and Lower Divider Impedance (RU||RL), sets the
time constant for the start up ramp when transitioning from
S3 to S0/S1/S2.
The minimum value for CSS can be found using
Equation 2:
I
PEAK
I
OCSET xROCSET
r
DS ON
()
-------------------------------------------------
=
(EQ. 1)
C
SS
C
VTTOUT VDDQ
10 2A R
U
R
L
||
⋅⋅
------------------------------------------------
>
(EQ. 2)
ISL6532A


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