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ISL6742AAZA Datasheet(PDF) 9 Page - Intersil Corporation |
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ISL6742AAZA Datasheet(HTML) 9 Page - Intersil Corporation |
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9 / 18 page  9 FN9183.1 July 25, 2005 OUTAN and OUTBN - These outputs are the complements of OUTA and OUTB, respectively. These outputs are suitable for control of synchronous rectifiers. The phase relationship between each output and its complement is set by a control voltage applied to VADJ. VADJ - A 0 - 5V control voltage applied to this input sets the relative delay or advance between OUTA/OUTB and OUTAN/OUTBN. Voltages below 2.425V result in OUTAN/OUTBN being advanced relative to OUTA/OUTB. Voltages above 2.575V result in OUTAN/OUTBN being delayed relative to OUTA/OUTB. A voltage of 2.50V ±75mV results in zero phase difference. A weak internal 50% divider from VREF results in no phase delay if this input is left floating. The range of phase delay/advance is either zero or 40 to 300ns with the phase differential increasing as the voltage deviation from 2.5V increases. The relationship between the control voltage and phase differential is non-linear. The gain ( ∆t/∆V) is low for control voltages near 2.5V and rapidly increases as the voltage approaches the extremes of the control range. This behavior provides the designer increased accuracy when selecting a shorter delay/advance duration. IOUT - Output of the 4X buffer amplifier of the sample and hold circuitry that captures and averages the CS signal. RAMP - This is the input for the sawtooth waveform for the PWM comparator. The RAMP pin is shorted to GND at the termination of the PWM signal. A sawtooth voltage waveform is required at this input. For current-mode control this pin is connected directly to CS and the current loop feedback signal is applied to both inputs. For voltage-mode control, the oscillator sawtooth waveform may be buffered and used to generate an appropriate signal, or RAMP may be connected to the input voltage through an RC network for voltage feed forward control, or RAMP may be connected to VREF through an RC network to produce the desired sawtooth waveform. FB - FB is the inverting input to the error amplifier (EA). The amplifier may be used as the error amplifier for voltage feedback or used as the average current limit amplifier (IEA). If the amplifier is not used, FB should be grounded. VERR - The VERR pin is the output of the error amplifier and controls the inverting input of the PWM comparator. Feedback compensation components connect between VERR and FB. There is a nominal 1mA pull-up current source connected to VERR. Soft-start is implemented as a voltage clamp on the VERR signal. The outputs, OUTA and OUTB, reduce to 0% duty cycle when VERR is pulled below 0.6V. OUTAN and OUTBN, the complements of OUTA and OUTB, respectively, go to 100% duty cycle when this occurs. SS - Connect the soft-start timing capacitor between this pin and GND to control the duration of soft-start. The value of the capacitor determines the rate of increase of the duty cycle during start-up. Although no minimum value of capacitance is required, it is recommended that a value of at least 100pF be used for noise immunity. SS may also be used to inhibit the outputs by grounding through a small transistor in an open collector/drain configuration. Functional Description Features The ISL6742 PWM is an excellent choice for low cost bridge and push-pull topologies in applications requiring accurate duty cycle and deadtime control. With its many protection and control features, a highly flexible design with minimal external components is possible. Among its many features are current- or voltage-mode control, adjustable soft-start, peak and average overcurrent protection, thermal protection, synchronous rectifier outputs with variable delay/advance timing, and adjustable oscillator frequency. Oscillator The ISL6742 oscillator, with a programmable frequency range to 2MHz, is set with only an external resistor and capacitor. The switching period is the sum of the timing capacitor charge and discharge durations. The charge duration is determined by CT and a fixed 200 µA internal current source. The discharge duration is determined by RTD and CT. where TC and TD are the charge and discharge times, respectively, TSW is the oscillator period, and FSW is the oscillator frequency. Since the ISL6742 is a double-ended controller, one output switching cycle requires two oscillator cycles. The actual charge and discharge times will be slightly longer than calculated due to internal propagation delays of approximately 10ns/transition. This delay adds directly to the switching duration, but also causes slight overshoot of the timing capacitor peak and valley voltage thresholds, effectively increasing the peak-to-peak voltage on the timing capacitor. Additionally, if very low discharge currents are used, there will be increased error due to the input impedance at the CT pin. TC 11.5 10 ⋅ 3 CT ⋅ ≈ S (EQ. 1) TD 0.06 RTD CT ⋅⋅ () 50 10 9 – ⋅ + ≈ S (EQ. 2) TSW TC TD + 1 FSW ------------ == S (EQ. 3) ISL6742 |
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