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ISL9105 Datasheet(PDF) 8 Page - Intersil Corporation

Part No. ISL9105
Description  600mA Low Quiescent Current 1.6MHz High Efficiency Synchronous Buck Regulator
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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ISL9105 Datasheet(HTML) 8 Page - Intersil Corporation

 
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8
FN6415.1
February 13, 2007
The output voltage is regulated by controlling the reference
voltage to the current loop. The bandgap circuit outputs a
0.8V reference voltage to the voltage control loop. The
feedback signal comes from the FB pin. The soft-start block
only affects the operation during the start-up and will be
discussed separately in the “Soft-Start-Up” on page 9. The
error amplifier is a transconductance amplifier, which
converts the voltage error signal to a current output. The
voltage loop is internally compensated by a RC network. The
maximum EAMP voltage output is precisely clamped to the
bandgap voltage (1.172V).
SKIP Mode
The ISL9105 enters a pulse-skipping mode at light load to
minimize the switching loss by reducing the effective
switching frequency. Figure 16 illustrates the skip-mode
operation. A zero-cross sensing circuit (as shown in
Figure 15) monitors the N-Channel MOSFET current for zero
crossing. When the N-Channel MOSFET current is detected
crossing zero for 8 consecutive cycles, the regulator enters
the skip mode. During the 8 consecutive cycles, the inductor
current is allowed to be negative. The internal counter is
reset to zero when the sensed N-Channel MOSFET current
does not cross zero in any cycle within the 8 consecutive
cycles.
Once ISL9105 enters SKIP mode, the pulse modulation
starts being controlled by the SKIP comparator shown in
Figure 15. Each pulse cycle is still synchronized by the PWM
clock. The P-Channel MOSFET is turned on at the rising
edge of the clock and turned off when its current reaches
20% of the peak current limit. As the average inductor
current in each cycle is higher than the average current of
the load, the output voltage rises cycle over cycle. When the
output voltage reaches 1.5% above the nominal voltage, the
P-Channel MOSFET is turned off immediately and the
inductor current is fully discharged to zero and remains zero.
The output voltage reduces gradually due to the load current
discharging the output capacitor. When the output voltage
drops to the nominal voltage, the P-Channel MOSFET will
be turned on again, repeating the previous operations.
The regulator resumes PWM mode operation when the
output voltage drops 1.5% below the nominal voltage.
Enable
The enable (EN) input allows user to control the turn-on and
turn-off of the regulator for purposes such as power-up
sequencing. When the regulator is enabled, there is a
typically a 600µs delay for waking up the internal reference
circuit, then the soft start-up begins. When the regulator is
disabled, the P-MOSFET is turned off immediately and the
output capacitor is discharged.
POR Signal
The ISL9105 offers a Power-On Reset (POR) signal. When
the output voltage is not within a power-good window, the
POR pin outputs an open-drain low signal (Figure 15), which
can be used to reset the microprocessor. When the output
voltage is within a power-good window, a power-good signal
is issued to turn off the open-drain POR pin. The rising edge
of the POR output is delayed by 216ms(typical) from the
time the power-good signal is issued.
Mode Selection
MODE pin is provided on ISL9105 to select the operation
mode. When it is driven to logic low or shorted to ground, the
regulator operates in the forced PWM mode. The forced
PWM mode remains the fixed PWM frequency (typically
1.6MHz) at all load conditions.
When the MODE pin is driven to logic high or connected to
input voltage VIN, the regulator operates in either SKIP
mode or fixed PWM mode depending upon the load
condition.
FIGURE 15. PWM OPERATION WAVEFORMS
VEAMP
VCSA1
DUTY
CYCLE
IL
VOUT
CLOCK
IL
VOUT
NOMINAL + 1.5%
NOMINAL
CURRENT LIMIT
LOAD CURRENT
0
8 CYCLES
FIGURE 16.
SKIP MODE OPERATION WAVEFORMS
ISL9105


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