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ISL9105 Datasheet(PDF) 7 Page - Intersil Corporation

Part No. ISL9105
Description  600mA Low Quiescent Current 1.6MHz High Efficiency Synchronous Buck Regulator
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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ISL9105 Datasheet(HTML) 7 Page - Intersil Corporation

 
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7
FN6415.1
February 13, 2007
ISL9105
Block Diagram
Theory of Operation
The ISL9105 is a step-down switching regulator optimized
for battery-powered handheld applications. The regulator
operates at 1.6MHz fixed switching frequency under heavy
load condition to allow small external inductor and capacitors
to be used for minimal printed-circuit board (PCB) area. At
light load, the regulator reduces the switching frequency,
unless forced to the fixed frequency, to minimize the
switching loss and to maximize the battery life. The
quiescent current when the output is not loaded is typically
only 25
μA. The supply current is typically only 0.1μA when
the regulator is shut down.
PWM Control Scheme
The ISL9105 employs the current-mode pulse-width
modulation (PWM) control scheme for fast transient
response and pulse-by-pulse current limiting. Figure 15
shows the block diagram. The current loop consists of the
oscillator, the PWM comparator COMP, current sensing
circuit, and the slope compensation for the current loop
stability. The current sensing circuit consists of the
resistance of the P-Channel MOSFET when it is turned on
and the Current Sense Amplifier (CSA). The control
reference for the current loops comes from the Error
Amplifier (EAMP) of the voltage loop.
The PWM operation is initialized by the clock from the
oscillator. The P-Channel MOSFET is turned on at the
beginning of a PWM cycle and the current in the P-Channel
MOSFET starts ramping up. When the sum of the CSA
output and the compensation slope reaches the control
reference of the current loop, the PWM comparator COMP
sends a signal to the PWM logic to turn off the P-Channel
MOSFET and to turn on the N-Channel MOSFET. The N-
Channel MOSFET remains on till the end of the PWM cycle.
Figure 15 shows the typical operating waveforms during the
PWM operation. The dotted lines illustrate the sum of the
compensation ramp and the CSA output.
PHASE
+
+
CSA1
+
+
OCP
REF1
REF2
SKIP
+
+
Slope
COMP
SLOPE
Soft
START
SOFT
0.8V
EAMP
COMP
PWM/PFM
LOGIC
CONTROLLER
PROTECTION
DRIVER
FB
+
REF3
REF4
POR
SHUTDOWN
VIN
GND
OSCILLATOR
+
BANDGAP
SCP
+
REF5
EN
SHUTDOWN
POR
DELAY
RSI
ZERO CROSS
SENSING
MODE


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