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ISL6112 Datasheet(PDF) 19 Page - Intersil Corporation

Part # ISL6112
Description  Dual Slot PCI-Express Power Controller
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL6112 Datasheet(HTML) 19 Page - Intersil Corporation

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FN6456.0
September 28, 2007
ISL6112 Register Set and Programmer’s Model
Detailed Register Descriptions
Control Register, Slot A (CNTRLA)
8-Bits, Read/Write
TABLE 4. ISL6112 REGISTER ADDRESSES
TARGET REGISTER
COMMAND BYTE VALUE
POWER-ON
DEFAULT
LABEL
DESCRIPTION
READ
WRITE
CNTRLA
Control Register Slot A
02h
02h
00h
CNTRLB
Control Register Slot B
03h
03h
00h
STATA
Slot A Status
04h
04h
00h
STATB
Slot B Status
05h
05h
00h
CS
Common Status Register
06h
06h
xxxx 0000b
Reserved
Reserved/Do Not Use
07h - FFh
07h - FFh
Undefined
TABLE 5. CONTROL REGISTER, SLOT A (CNTRLA)
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
read-only
read-only
read only
read only
read-only
read/write
read/write
read/write
AUXAPG
MAINAPG
Reserved
Reserved
Reserved
FORCE_A
ENABLE
MAINA
VAUXA
BIT(s)
FUNCTION
OPERATION
AUXAPG
AUX output power-good status, Slot A
1 = Power-is-Good (VAUXA Output is above its UVLO
threshold)
MAINAPG
MAIN output power-good status, Slot A
1 = Power-is-Good (MAINA Outputs are above their UVLO
thresholds)
D[5]
Reserved
Always read as zero
D[4]
Reserved
Always read as zero
D[3]
Reserved
Always read as zero
FORCE_A
ENABLE
Allows or inhibits the operation of the FORCE_ONA input pin
0 = FORCE_ONA is enabled
1 = FORCE_ONA is disabled
MAINA
MAIN enable control, Slot A
0 = Off, 1 = On
VAUXA
VAUX enable control, Slot A
0 = Off, 1 = On
Power-Up Default Value:
0000 0000b = 00h
Read Command_Byte Value (R/W):
0000 0010b = 02h
The power-up default value is 00h. Slot is disabled upon power-up, i.e., all supply outputs are off.
NOTES:
6. The state of the PWRGDA pin is the logical AND of the values of the AUXAPG and the MAINAPG bits, except when FORCE_ONA is asserted.
If FORCE_ONA is asserted (the pin is pulled low), and FORCE_AENABLE is set to a logic zero, the PWRGDA pin will be unconditionally
forced to its open-drain (“Power Not Good”) state.
7. The values of the MAINAPG and AUXAPG register bits are not affected by FORCE_ONA, but will instead continue to read as high if power is
“Good,” and as low if the conditions which indicate that power is good are not met.
ISL6112


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