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ISL6261IR7Z-T Datasheet(PDF) 7 Page - Intersil Corporation |
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ISL6261IR7Z-T Datasheet(HTML) 7 Page - Intersil Corporation |
7 / 34 page 7 FN9251.1 September 27, 2006 VSUM This pin is connected to one terminal of the capacitor in the current sensing R-C network. VIN Power stage input voltage. It is used for input voltage feed forward to improve the input line transient performance. VSS Signal ground. Connect to controller local ground. VDD 5V control power supply. BOOT Upper gate driver supply voltage. An internal bootstrap diode is connected to the VCCP pin. UGATE The upper-side MOSFET gate signal. PHASE The phase node. This pin should connect to the source of upper MOSFET. VSSP The return path of the lower gate driver. LGATE The lower-side MOSFET gate signal. VCCP 5V power supply for the gate driver. NC Not connected. Ground this pin in the practical layout. VID0, VID1, VID2, VID3, VID4, VID5, VID6 VID input with VID0 as the least significant bit (LSB) and VID6 as the most significant bit (MSB). VR_ON VR enable pin. A logic high signal on this pin enables the regulator. DPRSLPVR Deeper sleep enable signal. A logic high indicates that the microprocessor is in Deeper Sleep Mode and also indicates a slow Vo slew rate with 41 μA discharging or charging the SOFT cap. DPRSTP# Deeper sleep slow wake up signal. A logic low signal on this pin indicates that the microprocessor is in Deeper Sleep Mode. CLK_EN# Digital output for system PLL clock. Goes active 20µs after PGD_IN is active and Vcore is within 10% of boot voltage. 3V3 3.3V supply voltage for CLK_EN#. PGOOD Power good open-drain output. Needs to be pulled up externally by a 680 resistor to VCCP or 1.9k to 3.3V. ISL6261 |
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