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AT32UC3B1128-Z1UT Datasheet(PDF) 9 Page - ATMEL Corporation |
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AT32UC3B1128-Z1UT Datasheet(HTML) 9 Page - ATMEL Corporation |
9 / 676 page 9 32059I–06/2010 AT32UC3B 4.2.2 JTAG Port Connections If the JTAG is enabled, the JTAG will take control over a number of pins, irrespective of the I/O Controller configuration. 4.2.3 Nexus OCD AUX port connections If the OCD trace system is enabled, the trace system will take control over a number of pins, irre- spectively of the PIO configuration. Two different OCD trace pin mappings are possible, depending on the configuration of the OCD AXS register. For details, see the AVR32 UCTechni- cal Reference Manual. 4.2.4 Oscillator Pinout The oscillators are not mapped to the normal A, B or C functions and their muxings are con- trolled by registers in the Power Manager (PM). Please refer to the power manager chapter for more information about this. 55 PB09 GPIO 41 SSC - TX_CLOCK USART1 - RI EIC - SCAN[7] ABDAC - DATAN[1] 57 PB10 GPIO 42 SSC - TX_DATA TC - A2 USART0 - RXD 58 PB11 GPIO 43 SSC - TX_FRAME_SYNC TC - B2 USART0 - TXD Table 4-1. GPIO Controller Function Multiplexing Table 4-2. JTAG Pinout 64QFP/QFN 48QFP/QFN Pin name JTAG pin 22 TCK TCK 33 PA00 TDI 44 PA01 TDO 55 PA02 TMS Table 4-3. Nexus OCD AUX port connections Pin AXS=0 AXS=1 EVTI_N PB05 PA14 MDO[5] PB04 PA08 MDO[4] PB03 PA07 MDO[3] PB02 PA06 MDO[2] PB01 PA05 MDO[1] PB00 PA04 MDO[0] PA31 PA03 EVTO_N PA15 PA15 MCKO PA30 PA13 MSEO[1] PB06 PA09 MSEO[0] PB07 PA10 |
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