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UCC28250 Datasheet(PDF) 13 Page - Texas Instruments

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Part No. UCC28250
Description  Advanced PWM Controller With Pre-Bias Operation
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

UCC28250 Datasheet(HTML) 13 Page - Texas Instruments

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( )
d SP
SW
T
1
T
2
f
R
33.2pF
-
´
=
0
200
RT Resistor - kW
0
1200
2000
100
OSCILLATOR FREQUENCY
vs
RT RESISTOR
40
20
120
180
1600
800
400
60
80
140 160
200
600
1000
1400
1800
T
D(ps) = 40 ns
T
D(ps) = 100 ns
UCC28250
www.ti.com
SLUSA29B – APRIL 2010 – REVISED OCTOBER 2010
RT (Oscillator Frequency Set and Synchronization) (15/2)
The UCC28250 oscillator frequency is set by an external resistor connected between the RT pin and ground.
Switching frequency selection is a trade-off between efficiency and component size. Based on the selected
switching frequency, the programming resistor value can be calculated as:
(3)
In this equation, fSW is the switching frequency and TD(sp) is the dead time between synchronous rectifier turn-off
to primary switch turn-on. TD(sp) is set by an external resistor between the SP pin and ground (refer to the SP pin
description).
Each output (OUTA, OUTB, SRA, SRB) switches at half the oscillator frequency (fSW = ½ x fOSC). Figure 6 shows
the relationship between RT and fOSC at certain TD(sp) and can be used to program oscillator frequency
accordingly.
Figure 6. Oscillator Frequency FOSC vs External Resistance of RT at TD(ps) = 40 ns and 100 ns
The UCC28250 can be synchronized to an external clock by applying an external clock source to the RT pin.
Synchronization helps with parallel operation and/or preventing beat frequency noise. The UCC28250
synchronizes its internal oscillator to an external frequency source ranging from 170 kHz to 2.3 MHz, which is
equivalent to an 85-kHz to 1.15-MHz switching frequency. The internal oscillator frequency is clamped to 170
kHz during synchronization if the external source frequency drops below 170 kHz.
The UCC28250 aligns the turn-on of primary outputs OUTA and OUTB to the falling edge of the synchronizing
signal, as shown in Figure 7. If the frequency source is from the gate outputs of another half bridge controller,
interleaving can be achieved. The interleaving angle is determined by the frequency source’s duty cycle. When a
50% duty cycle is applied, optimal interleaving is achieved, and EMI filters can be minimized.
Copyright © 2010, Texas Instruments Incorporated
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