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UCC28250 Datasheet(PDF) 12 Page - Texas Instruments |
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UCC28250 Datasheet(HTML) 12 Page - Texas Instruments |
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12 / 50 page  2 R 10 k > W 1 1 6 s C R m = UVLO EN 0.3V SS CLK Enable Signal EN C1 R1 R2 UCC28250 EN Enable Signal (a) (b) UCC28250 SLUSA29B – APRIL 2010 – REVISED OCTOBER 2010 www.ti.com A pulse signal may also be applied to the EN pin. Pulse-enable operation is shown on Figure 4. If the EN falling edge happens before the SS voltage reaches 0.3 V, the enable signal at EN pin is considered as a pulse. In this case, the next rising edge at EN pin disables the controller. If the falling edge of the first pulse at EN pin happens after SS rises to 0.3 V, the UCC28250 interprets the pulse enable as a level enable, and an external solution as shown on Figure 5 (a) can be used to reduce the pulse width. In this circuit, R2 is used to limit the current (especially the negative current) through the internal ESD cell. Figure 5 (b) illustrates the waveforms based on this solution. To prevent false trigger by noises, the pulse at the EN pin must be at least 2.25 V (minimum) high and 3 µs wide to be considered valid. Choose the R1, R2, and C values based on the following equations: Choose R2 based on the current limit requirement from the device. (1) Choose R1 arbitrarily but much smaller than R2 and choose C1 according to the time constant requirement to generate longer than 3-µs pulse. (2) If enable function is not used, pull EN pin to VREF. Figure 4. Pulse Enable at EN Pin Figure 5. An External Solution to Generate Enable Pulses for Pulse Enable 12 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): UCC28250 |
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