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SX1512BIULTRT Datasheet(PDF) 18 Page - Semtech Corporation

Part No. SX1512BIULTRT
Description  World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine
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Maker  SEMTECH [Semtech Corporation]
Homepage  http://www.semtech.com
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SX1512BIULTRT Datasheet(HTML) 18 Page - Semtech Corporation

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ADVANCED COMMUNICATIONS & SENSING
Rev 3 – 9
th Sept. 2010
18
www.semtech.com
SX1510B/SX1511B/SX1512B
World’s Lowest Voltage Level Shifting GPIO
with LED Driver and Keypad Engine
Figure 13 – Level Shifter Max Frequency Calculation Data
4.6.4
Polarity Inverter
Each IO’s polarity can be individually inverted by setting corresponding bit in RegPolarity register. Please note
that polarity inversion can also be combined with level shifting feature.
4.7
Interrupt (NINT)
At start-up, the transition detection logic is reset, and NINT is released to a high-impedance state. The interrupt
mask register is set to 0xFF, disabling the interrupt output for transitions on all I/O ports. The transition flags are
cleared to indicate no data changes.
An interrupt NINT can be generated on any programmed combination of I/Os rising and/or falling edges through
the RegInterruptMask and RegSense registers.
If needed, the I/Os which triggered the interrupt can then be identified by reading RegInterruptSource register.
When NINT is low (i.e. interrupt occurred), it can be reset back high (i.e. cleared) by writing 0xFF in
RegInterruptSource (this will also clear corresponding bits in RegEventStatus register).
The interrupt can also be cleared automatically when reading RegData register (Cf. RegMisc)
Example: We want to detect rising edge of I/O[1] on SX1511B (NINT will go low).
SX1512B Digital Core Delay vs. Supply Voltage
14
16
18
20
22
24
26
28
1
1.5
2
2.5
3
3.5
VDDM (V)
Typical
Worst Case
IO Input Delay vs. Supply Voltage
0.000
1.000
2.000
3.000
4.000
5.000
6.000
7.000
8.000
9.000
10.000
1.000
1.500
2.000
2.500
3.000
3.500
VCCx (V)
Typical
Worst Case
SX1511B Digital Core Delay vs. Supply Voltage
14
16
18
20
22
24
26
28
1
1.5
2
2.5
3
3.5
VDDM (V)
Typical
Worst Case
IO Output Delay vs. Supply Voltage ( LowDriveEn=0, 20pF Load)
0.000
20.000
40.000
60.000
80.000
100.000
120.000
140.000
1.000
1.500
2.000
2.500
3.000
3.500
VCCx (V)
Typical
Worst Case
IO Output Delay vs. Supply Voltage (LowDriveEn=1, 20pF Load)
0.000
20.000
40.000
60.000
80.000
100.000
120.000
140.000
1.000
1.500
2.000
2.500
3.000
3.500
VCCx (V)
Typical
Worst Case


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