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SST25WF010-40-5I-SAF Datasheet(PDF) 5 Page - Silicon Storage Technology, Inc |
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SST25WF010-40-5I-SAF Datasheet(HTML) 5 Page - Silicon Storage Technology, Inc |
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5 / 32 page  Data Sheet 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040 5 ©2009 Silicon Storage Technology, Inc. S71328-08-000 11/09 Reset/Hold Mode The RST#/HOLD# pin provides either a hardware reset or a hold pin. From power-on, the RST#/HOLD# pin defaults as a hardware reset pin (RST#). The Hold mode for this pin is a user selected option where an Enable-Hold instruction enables the Hold mode. Once selected as a hold pin (HOLD#), the RST#/HOLD# pin will be configured as a HOLD# pin, and goes back to RST# pin only after a power- off and power-on sequence. Reset If the RST#/HOLD# pin is used as a reset pin, RST# pin provides a hardware method for resetting the device. Driving the RST# pin high puts the device in normal operating mode. The RST# pin must be driven low for a minimum of TRST time to reset the device. The SO pin is in high imped- ance state while the device is in reset. A successful reset will reset the status register to its power-up state. See Table 4 for default power-up modes. A device reset during an active Program or Erase operation aborts the operation and data of the targeted address range may be corrupted or lost due to the aborted erase or program operation. The device exits AAI Programming Mode in progress and places the SO pin in high impedance state. FIGURE 4: Reset Timing Diagram TABLE 2: Reset Timing Parameters Symbol Parameter Min Max Units TRST Reset Pulse Width 100 ns TRHZ Reset to High-Z Output 107 ns TRECR Reset Recovery from Read 100 ns TRECP Reset Recovery from Program 10 µs TRECE Reset Recovery from Erase 1 ms T2.1328 1328 Fx4.0 CE# SO SI SCK RST# TRECR TRECP TRECE TRST TRHZ |
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