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SST26VF032-80-5I-S2E Datasheet(PDF) 7 Page - Silicon Storage Technology, Inc |
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SST26VF032-80-5I-S2E Datasheet(HTML) 7 Page - Silicon Storage Technology, Inc |
7 / 39 page ©2010 Silicon Storage Technology, Inc. S71359-05-000 06/10 7 Serial Quad I/O (SQI) Flash Memory SST26VF016 / SST26VF032 Data Sheet Device Protection The SST26VF016/032 have a Block-Protection register which provides a software mechanism to write- lock the array and write-lock, and/or read-lock, the parameter blocks. The Block-Protection Register is 48/80 bits wide per device: two bits each for the eight 8 KByte parameter blocks (write-lock and read- lock), and one bit each for the remaining 32 KByte and 64 KByte overlay blocks (write-lock). See Tables 8 - 9 for address range protected per register bit. Each bit in the Block-Protection Register can be written to a ‘1’ (protected) or ‘0’ (unprotected). For the parameter blocks, the most significant bit is for read-lock, and the least significant bit is for write-lock. Read- locking the parameter blocks provides additional security for sensitive data after retrieval (e.g., after initial boot). If a block is read-locked all reads to the block return data 00H. All blocks are write-locked and read- unlocked after power-up or reset. The Write Block Locking Register command is a two cycle command requiring Write-Enable (WREN) to be executed prior to the Write Block-Protection Register command. Figure 6: Block Locking Memory Map 1359 F40.2 Top of Memory Block 8 KByte 8 KByte 8 KByte 8 KByte 32 KByte 64 KByte 64 KByte 64 KByte 32 KByte 8 KByte 8 KByte 8 KByte 8 KByte Read Lock Write Lock Read Lock Write Lock Write Lock Bottom of Memory Block |
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