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SST25LF020A-33-4E-QAE Datasheet(PDF) 4 Page - Silicon Storage Technology, Inc |
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SST25LF020A-33-4E-QAE Datasheet(HTML) 4 Page - Silicon Storage Technology, Inc |
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4 / 25 page  4 Data Sheet 2 Mbit SPI Serial Flash SST25LF020A ©2010 Silicon Storage Technology, Inc. S71242-07-000 01/10 PRODUCT IDENTIFICATION MEMORY ORGANIZATION The SST25LF020A SuperFlash memory array is orga- nized in 4 KByte sectors with 32 KByte overlay blocks. DEVICE OPERATION The SST25LF020A is accessed through the SPI (Serial Peripheral Interface) bus compatible protocol. The SPI bus consist of four control lines; Chip Enable (CE#) is used to select the device, and data is accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). The SST25LF020A supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference between the two modes, as shown in Figure 3, is the state of the SCK signal when the bus master is in Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock signal. FIGURE 3: SPI Protocol TABLE 2: Product Identification Address Data Manufacturer’s ID 00000H BFH Device ID SST25LF020A 00001H 43H T2.0 1242 1242 F02.0 MODE 3 SCK SI SO CE# MODE 3 DON'T CARE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1Bit 0 MODE 0 MODE 0 HIGH IMPEDANCE MSB MSB |
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