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SST25VF032B-66-4I-S2F Datasheet(PDF) 3 Page - Silicon Storage Technology, Inc |
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SST25VF032B-66-4I-S2F Datasheet(HTML) 3 Page - Silicon Storage Technology, Inc |
3 / 28 page Data Sheet 32 Mbit SPI Serial Flash SST25VF032B 3 ©2009 Silicon Storage Technology, Inc. S71327-03-000 05/09 PIN DESCRIPTION FIGURE 2: Pin Assignments for 8-Lead SOIC TABLE 1: Pin Description Symbol Pin Name Functions SCK Serial Clock To provide the timing of the serial interface. Commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. SI Serial Data Input To transfer commands, addresses, or data serially into the device. Inputs are latched on the rising edge of the serial clock. SO Serial Data Output To transfer data serially out of the device. Data is shifted out on the falling edge of the serial clock. RY/BY# Ready / Busy pin Flash busy status pin in AAI mode if SO is configured as a hardware RY/BY# pin. CE# Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of any command sequence. WP# Write Protect The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register. HOLD# Hold To temporarily stop serial communication with SPI flash memory without resetting the device. VDD Power Supply To provide power supply voltage: 2.7-3.6V VSS Ground T1.0 1327 1 2 3 4 8 7 6 5 CE# SO WP# VSS VDD HOLD# SCK SI Top View 1327 8-SOIC P1.0 Notes: 1. In AAI mode, the SO pin can act as a RY/BY# pin when configured as a ready/busy status pin. See “End-of- Write Detection” on page 11 for details. 1 2 3 4 8 7 6 5 CE# SO WP# VSS Top View VDD HOLD# SCK SI 1327 8-WSON P1.0 |
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