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CC2510F32RSP Datasheet(PDF) 10 Page - Texas Instruments

Part No. CC2510F32RSP
Description  Low-Power SoC (System-on-Chip) with MCU, Memory, 2.4 GHz RF Transceiver, and USB Controller
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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CC2510F32RSP Datasheet(HTML) 10 Page - Texas Instruments

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CC2510Fx / CC2511Fx
SWRS055F
Page 10 of 241
6
Electrical Specifications
6.1
Current Consumption
TA = 25°C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the
CC2510EM reference design ([1]).
Parameter
Min
Typ
Max
Unit
Condition
4.8
mA
System clock running at 26 MHz.
4.6
mA
System clock running at 24 MHz.
Active mode, full
speed (high speed
crystal oscillator)
1.
Low CPU activity.
Digital regulator on. High speed crystal oscillator and low power
RCOSC running. No peripherals running.
Low CPU activity: No flash access (i.e. only cache hit), no RAM
access
Active mode, full
speed (HS
RCOSC)
1.
Low CPU activity.
2.5
mA
System clock running at 13 MHz.
Digital regulator on. HS RCOSC and low power RCOSC running. No
peripherals running.
Low CPU activity: No flash access (i.e. only cache hit), no RAM
access
Digital regulator on. High speed crystal oscillator and low power
RCOSC running. Radio in RX mode (sensitivity optimized
MDMCFG2.DEM_DCFILT_OFF=0)
19.8
20.6
17.1
mA
mA
mA
2.4 kBaud, input at sensitivity limit, system clock running at 26 MHz.
2.4 kBaud, input at sensitivity limit, system clock running at 24 MHz.
2.4 kBaud, input at sensitivity limit, system clock running at 203 kHz.
19.8
mA
2.4 kBaud, input well above sensitivity limit, system clock running at
26 MHz.
21.5
22.1
18.8
mA
mA
mA
10 kBaud, input at sensitivity limit, system clock running at 26 MHz.
10 kBaud, input at sensitivity limit, system clock running at 24 MHz.
10 kBaud, input at sensitivity limit, system clock running at 203 kHz.
19.0
mA
10 kBaud, input well above sensitivity limit, system clock running at
26 MHz.
22.9
22.7
20.5
mA
mA
mA
250 kBaud, input at sensitivity limit, system clock running at 26 MHz.
250 kBaud, input at sensitivity limit, system clock running at 24 MHz.
250 kBaud, input at sensitivity limit, system clock running at 1.625
MHz.
19.6
mA
250 kBaud, input well above sensitivity limit, system clock running at
26 MHz. See Figure 2 for typical variation over operating conditions
19.7
20.8
17.5
mA
mA
mA
500 kBaud, input at sensitivity limit, system clock running at 26 MHz.
500 kBaud, input at sensitivity limit, system clock running at 24 MHz.
500 kBaud, input at sensitivity limit, system clock running at 3.25
MHz.
16.7
mA
500 kBaud, input well above sensitivity limit
Digital regulator on. High speed crystal oscillator and low power
RCOSC running. Radio in RX mode (current optimized
MDMCFG2.DEM_DCFILT_OFF=1)
17.4
mA
2.4 kBaud, input at sensitivity limit, system clock running at 26 MHz.
14.7
mA
2.4 kBaud, input at sensitivity limit, system clock running at 203 kHz.
Active mode with
radio in RX
17.4
mA
2.4 kBaud, input well above sensitivity limit, system clock running at
26 MHz.
1
Note: In order to reduce the current consumption in active mode, the clock speed can be reduced by
setting
CLKCON.CLKSPD≠000 (see section 13.1 for details). Figure 1 shows typical current
consumption in active mode for different clock speeds


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