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R5F64177HPFD Datasheet(PDF) 78 Page - Renesas Technology Corp |
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R5F64177HPFD Datasheet(HTML) 78 Page - Renesas Technology Corp |
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78 / 114 page  REJ03B0254-0110 Rev.1.10 Page 78 of 111 Jun 23, 2010 R32C/117 Group 5. Electrical Characteristics Note: 1. This value is applicable only when the main clock oscillation is stable. Note: 1. This recovery time does not include the period until the main clock oscillator is stabilized. The CPU starts operating before the oscillator is stabilized. Figure 5.4 Clock Circuit Timing Table 5.12 Electrical Characteristics of Oscillator (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta =Topr, unless otherwise noted) Symbol Characteristics Measurement condition Value Unit Min. Typ. Max. fSO(PLL) PLL clock self-oscillation frequency 35 50 65 MHz tLOCK(PLL) PLL lock time (1) 1ms tjitter(p-p) PLL jitter period (p-p) 2.0 ns f(OCO) On-chip oscillator frequency 62.5 125 250 kHz Table 5.13 Electrical Characteristics of Clock Circuitry (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta =Topr, unless otherwise noted) Symbol Characteristics Measurement condition Value Unit Min. Typ. Max. trec(WAIT) Recovery time from wait mode to low power mode 225 µs trec(STOP) Recovery time from stop mode (1) 225 µs t rec(STOP) Interrupt for exiting stop mode CPU clock Main clock oscillator output On-chip oscillator output Sub clock oscillator output On-chip oscillator output t rec(WAIT) Interrupt for exiting wait mode CPU clock Recovery time from stop mode t rec(STOP) Recovery time from wait mode to low power mode t rec(WAIT) |
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