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118A Datasheet(PDF) 89 Page - Renesas Technology Corp |
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118A Datasheet(HTML) 89 Page - Renesas Technology Corp |
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89 / 130 page  REJ03B0299-0100 Rev.1.00 Page 89 of 127 Jul 16, 2010 R32C/118A Group 5. Electrical Characteristics Note: 1. The device is operationally guaranteed under these operating conditions. Figure 5.1 Clock Cycle Time Table 5.5 Operating Conditions (4/5) (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta =Topr, unless otherwise noted) (1) Symbol Characteristic Value Unit Min. Typ. Max. f(XIN) Main clock oscillator frequency 416 MHz f(XRef) Reference clock frequency 24 MHz f(PLL) PLL clock oscillator frequency 96 128 MHz f(Base) Base clock frequency 64 MHz tc(Base) Base clock cycle time 15.625 ns f(CPU) CPU operating frequency 64 MHz tc(CPU) CPU clock cycle time 15.625 ns f(BCLK) Peripheral bus clock operating frequency 32 MHz tc(BCLK) Peripheral bus clock cycle time 31.25 ns f(PER) Peripheral clock source frequency 32 MHz f(XCIN) Sub clock oscillator frequency 32.768 62.5 kHz Base clock (Internal signal) t c(Base) Peripheral bus clock (Internal signal) t c(BCLK) CPU clock (Internal signal) t c(CPU) |
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