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ATTINY40-SUR Datasheet(PDF) 5 Page - ATMEL Corporation |
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ATTINY40-SUR Datasheet(HTML) 5 Page - ATMEL Corporation |
5 / 216 page 5 8263A–AVR–08/10 ATtiny40 The resulting architecture is compact and code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATtiny40 provides the following features: 4K bytes of In-System Programmable Flash, 256 bytes of SRAM, twelve general purpose I/O lines, 16 general purpose working registers, an 8-bit Timer/Counter with two PWM channels, a 8/16-bit Timer/Counter, Internal and External Inter- rupts, an eight-channel, 10-bit ADC, a programmable Watchdog Timer with internal oscillator, a slave two-wire interface, a master/slave serial peripheral interface, an internal calibrated oscilla- tor, and four software selectable power saving modes. Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and interrupt system to continue functioning. ADC Noise Reduction mode minimizes switching noise during ADC conversions by stopping the CPU and all I/O modules except the ADC. In Power-down mode registers keep their contents and all chip functions are disabled until the next interrupt or hardware reset. In Standby mode, the oscillator is running while the rest of the device is sleeping, allowing very fast start-up combined with low power consumption. The device is manufactured using Atmel’s high density non-volatile memory technology. The on- chip, in-system programmable Flash allows program memory to be re-programmed in-system by a conventional, non-volatile memory programmer. The ATtiny40 AVR is supported by a suite of program and system development tools, including macro assemblers and evaluation kits. |
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