6

©2009 Semtech Corp.

www.semtech.com

SC2595

PRELIMINARY

POWER MANAGEMENT

Overview

Overview

Overview

Overview

Overview

Double Data Rate (DDR) SDRAM was defined by JEDEC

1997. Its clock speed is the same as previous SDRAM

but data transfers speed is twice than previous SDRAM.

By now, the requirement voltage range is changed from

3.3V to 2.5V; the power dissipation is smaller than

SDRAM. For above reasons, it is very popular and widely

used in M/B, N/B, Video-cards, CD ROM drives, Disk

drives.

Regarding the DDR power management solution, there

are two topologies can be selected for system design-

ers. One is switching mode regulator that has bigger sink/

source current capability, but the cost is higher and the

board space needed is bigger. Another solution is linear

mode regulator, which costs less, and needs the less

board space. For two DIMM motherboards, system de-

signers usually choose the linear mode for DDR power

management solution.

Applications

TTTTTypical Application Cir

ypical Application Cir

ypical Application Cir

ypical Application Cir

ypical Application Circuits & W

cuits & W

cuits & W

cuits & W

cuits & Waaaaavvvvvef

ef

ef

ef

eforms

orms

orms

orms

orms

Two different application circuits are shown below in Fig-

ure 1 to Figure 2. Each circuit is designed for specific

condition. More details are described below. See Note

1. Below for recommended power up sequencing.

Application_1: Standar

Application_1: Standar

Application_1: Standar

Application_1: Standar

Application_1: Standard SS

d SS

d SS

d SS

d SSTL

TL

TL

TL

TL-2 Application

-2 Application

-2 Application

-2 Application

-2 Application

The AV

together for SSTL-2 application. It only needs a 2.5V

power rail for normal operation. System designer can

save the PCB space and reduce the cost. Please refer

to figures 3 to 4 for test waveforms.

Figure 1: Standard SSTL-2 application

Application Information

Application_2: Lower Power Loss Configuration

Application_2: Lower Power Loss Configuration

Application_2: Lower Power Loss Configuration

Application_2: Lower Power Loss Configuration

Application_2: Lower Power Loss Configuration

fffffor SS

or SS

or SS

or SS

or SSTL

TL

TL

TL

TL-2

-2

-2

-2

-2

If power loss is a major concern, separated the PV

the AV

operate at lower voltage (1.8V to 2.5V). If 2.5V voltage

is applied on AV

lower due to the lower operating voltage applied on the

PV

Please find the relative test result in Figures 5, 11

and 12.

Figure 2: Lower power loss for SSTL-2 application

Notes:

Notes:

Notes:

Notes:

Notes:

(1) Power up of AV

(a) The preferred mode of operation is when the

AV

single supply.

(b) If and when AV

separate to that of the V

the V

the V

rise simultaneously.

(c) If the AV

nected in a way such that, AV

precedes V

V

up, which may cause permanent damage to the

SDRAM.

Cin2

1uF

Cout1

220uF

VDD

Cin1

68uF

Cout2

10uF

SC2595

NC

1

GND

2

VSENSE

3

VREF

4

VDDQ

5

AVCC

6

PVCC

7

VTT

8

VTT

Cref

10nF

Csence

2.2uF

2.5V

1.25V

R1

5.1

R2

R

10uF

Cin2

1.25V

Csense

2.2uF

1uF

Cin2

Vin

2.5V

Cref

10nF

VTT

Cout1

220uF

SC2595

NC

1

GND

2

VSENSE

3

VREF

4

VDDQ

5

AVCC

6

PVCC

7

VTT

8

Cddq

1uF

VDD

1.8V to 2.5V

Cin1

68uF