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ATXMEGA384A1 Datasheet(PDF) 6 Page - ATMEL Corporation |
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ATXMEGA384A1 Datasheet(HTML) 6 Page - ATMEL Corporation |
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6 / 107 page  6 8067L–AVR–08/10 XMEGA A1 3.1 Block Diagram Figure 3-1. XMEGA A1 Block Diagram Power Supervision POR/BOD & RESET PORT A (8) PORT B (8) EVENT ROUTING NETWORK EVENT ROUTING NETWORK DMA Controller BUS Controller SRAM EBI ADCA DACA ACA DACB ADCB ACB OCD Int. Ref. PORT K (8) PORT J (8) PORT H (8) PDI CPU PH[0..7] PJ[0..7] PK[0..7] PA[0..7] PB[0..7]/ JTAG Watchdog Timer Watchdog Oscillator Interrupt Controller DATA BUS DATA BUS Prog/Debug Controller VCC GND Oscillator Circuits/ Clock Generation Oscillator Control Real Time Counter Event System Controller JTAG AREFA AREFB PDI_DATA RESET/ PDI_CLK PORT B Sleep Controller Flash EEPROM NVM Controller DES AES IRCOM PORT C (8) PC[0..7] PD[0..7] PE[0..7] PF[0..7] XTAL1 XTAL2 PR[0..1] TOSC1 TOSC2 PQ[0..3] PORT D (8) PORT E (8) PORT F (8) Tempref VCC/10 |
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