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S5N8952 Datasheet(PDF) 8 Page - Samsung semiconductor |
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S5N8952 Datasheet(HTML) 8 Page - Samsung semiconductor |
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8 / 18 page  8 S5N8952X ADSL Transceiver for NIC Preliminary Information (Rev.2.0) 5. Pin Description Table 1: Pin Description of the S5N8952X No Name I/O Description 178 RESET_N I System master reset (Active low) 168 XTAL_IN I 169 XTAL_OUT O System master clock (17.664MHz) 156 EXT_CLK I External clock for test (Float in normal mode) 172 PLL_FILT O PLL pump out (A 320pF capacitor between the pin and GNDA) 152 TEST_MODE_3 150 TEST_MODE_2 146 TEST_MODE_1 144 TEST_MODE_0 I Chip test mode [0] Normal mode, [1-15] Test mode 139 TEST_SCN_EN I Scan enable (Set to ‘0’ in normal mode) 93 TEST_IN I Test input (Float in normal mode) 92 TEST_OUT O Test output (Float in normal mode) 182 TX_SHOW O Tx showtime indicator (Active high. Connect to LED) 183 RX_SHOW O Rx showtime indicator (Active high. Connect to LED) 158 GP_OUT_1 157 GP_OUT_0 O General purpose outputs (Float if not needed) 165 BT_MODE_1 164 BT_MODE_0 I Boot mode [0] Reset, [1] Boot from host [2] Boot from JTAG, [3] Self-booting 161 NTR B ATM network timing reference (8KHz. Float if not needed) 200 PCI_AD_31 201 PCI_AD_30 203 PCI_AD_29 204 PCI_AD_28 207 PCI_AD_27 208 PCI_AD_26 1 PCI_AD_25 2 PCI_AD_24 9 PCI_AD_23 10 PCI_AD_22 12 PCI_AD_21 13 PCI_AD_20 16 PCI_AD_19 17 PCI_AD_18 20 PCI_AD_17 21 PCI_AD_16 44 PCI_AD_15 47 PCI_AD_14 48 PCI_AD_13 B PCI address data [31:0] |
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