OSD PROCESSOR FOR MONITOR

S5D2508A01

7

FUNCTIONAL DESCRIPTIONS

Data Transmission to the S5D2508A01

SCL line are shown in Figure 4. As shown in Figure 4, after the starting pulse, the slave address with R/W* bit and

an acknowledge are transmitted in sequence, an internal register address of the S5D2508A01 is followed. The first

8-bit byte is the upper 8bits of the register address. The lower 8bits of the register address are followed after the

second acknowledge. There is a data transmission format and are two address bit patterns in the S5D2508A01 as

following.

The slave address of the S5D2508A01 is BAH(in hexadecimal).

Data Transmission Format

Row Address -> Column Address -> Data Byte N -> Data Byte N+1 -> Data Byte N+2 -> ....

Address Bit Pattern for Display Registers Data

(a) Row Address Bit Pattern

R3 - R0: Valid Data for Row Address

(b) Column Address Bit Pattern

C4 - C0: Valid Data for Column Address

After addressing, data bytes are followed as the above data transmission format. The Figure 4 describes the data

Figure 4. SDA line and SCL line (Write Operation)

A15

A14

A13

A12

A11

A10

A9

A8

X

X

X

X

R3

R2

R1

R0

A7

A6

A5

A4

A3

A2

A1

A0

X

X

X

C4

C3

C2

C1

C0

SDA

A5

A4

A3

A2

A1

A0

A6

A7

A9

A8

A10

A11

A12

A13

A14

A15

R/W

SCL

START

IIC SLAVE ADDRESS

ACK

MSB ADDRESS

ACK

LSB ADDRESS

ACK

SCL

D1

D0

D2

D3

D4

D5

D6

D7

SDA

D1

D0

D2

D3

D4

D5

D6

D7

ACK

DATA BYTE N(MSB DATA)

ACK

STOP

ACK

DATA BYTE N(LSB DATA)

D1

D0

D2

D3

D4

D5

D6

D7

DATA BYTE N(MSB DATA)

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