Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

S3C72B5 Datasheet(PDF) 6 Page - Samsung semiconductor

Part No. S3C72B5
Description  The S3C72B5/C72B7/C72B9 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung A
Download  37 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  SAMSUNG [Samsung semiconductor]
Direct Link  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

S3C72B5 Datasheet(HTML) 6 Page - Samsung semiconductor

Back Button S3C72B5 Datasheet HTML 2Page - Samsung semiconductor S3C72B5 Datasheet HTML 3Page - Samsung semiconductor S3C72B5 Datasheet HTML 4Page - Samsung semiconductor S3C72B5 Datasheet HTML 5Page - Samsung semiconductor S3C72B5 Datasheet HTML 6Page - Samsung semiconductor S3C72B5 Datasheet HTML 7Page - Samsung semiconductor S3C72B5 Datasheet HTML 8Page - Samsung semiconductor S3C72B5 Datasheet HTML 9Page - Samsung semiconductor S3C72B5 Datasheet HTML 10Page - Samsung semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 37 page
background image
PRODUCT OVERVIEW
S3C72B5/C72B7/C72B9/P72B9
1-6
POWER DOWN
To reduce power consumption, there are two power-down modes: idle and stop. The IDLE instruction initiates idle
mode and the STOP instruction initiates stop mode.
In idle mode, only the CPU clock stops while peripherals and the oscillation source continue to operate normally.
Stop mode effects only the main system clock — a subsystem clock, if used, continues oscillating. In stop mode,
main system clock oscillation stops completely, halting all operations except for a few basic peripheral functions.
RESET or an interrupt can be used to terminate either idle or stop mode.
RESET
RESET
When a
RESET signal occurs during normal operation or during power-down mode, the CPU enters idle mode
when the reset operation is initiated. When the standard oscillation stabilization interval (31.3 ms at 4.19 MHz)
has elapsed, normal CPU operation resumes.
I/O PORTS
The S3C72B5/C72B7/C72B9 has 13 I/O ports. Pin addresses for all I/O ports are mapped in bank 15 of the RAM.
There are 4 input pins and 47 configurable I/O pins for a total of 51 I/O pins. The contents of I/O port pin latches
can be read, written, or tested at the corresponding address using bit manipulation instructions.
TIMERS and TIMER/COUNTERS
The timer function has four main components: an 8-bit basic interval timer, an 8-bit timer/counter, a 16-bit
timer/counter and a watch timer. The 8-bit basic timer generates interrupt requests at precise intervals, based on
the selected clock frequency and has watch-dog timer function.
The programmable 8-bit and 16-bit timer/counters are used for external event counting, generation of arbitrary
clock frequencies for output, and dividing external clock signals. The 16-bit timer/counter is the source of the
clock signal that is required to drive the serial I/O interface and configurable as two 8-bit timer/counters.
The watch timer has an 8-bit watch timer mode register, a clock selector and a frequency divider circuit. Its
functions include real-time and watch-time measurement, clock generation for the LCD controller and frequency
outputs for buzzer sound.
LCD DRIVER/CONTROLLER
The S3C72B5/C72B7/C72B9 can directly drive an up-to-1,280-dot LCD panel. The LCD function block has the
following components:
— RAM area for storing display data
— 80 segment output pins (SEG0–SEG79)
— Segment expandable circuit
— 16 common output pins (COM0–COM15)
— 5 operating power supply pins (V
LC1–VLC5)
— Sixteen level LCD contrast control circuit (software)
Frame frequency, LCD clock, duty, and segment pins used for display output are controlled by bit settings in the
8-bit mode register, LMOD. You use the 4-bit LCD control register, LCON, to turn the LCD display on and off,
and to control current supplied to the dividing resistors. Segment data are output using a direct memory access
method synchronized with the LCD frame frequency (f
LCD).
Using the main system clock, the LCD panel operates in idle mode; during stop mode, it is turned off. If a
subsystem clock is used as a clock source, the LCD panel will continue to operate during stop and idle modes.


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37 


Datasheet Download

Go To PDF Page

Related Electronics Part Number

Part No.DescriptionHtml ViewManufacturer
S3C7295 The S3C7295 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core SAM47 Samsung Arrangeable M 1  2  3  4  5  More Samsung semiconductor
S3C72C8 The S3C72C8 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core SAM47 Samsung Arrangeable M 1  2  3  4  5  More Samsung semiconductor
KS57C21116 The KS57C21116/C21124/C21132 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core SAM47 Sams 1  2  3  4  5  More Samsung semiconductor
S3C72F5 The S3C72F5 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core SAM47 Samsung Arrangeable M 1  2  3  4  5  More Samsung semiconductor
KS57C21832 The KS57C21832 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core SAM47 Samsung Arrangeabl 1  2  3  4  5  More Samsung semiconductor
S3C72G9 The S3C72G9 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core SAM47 Samsung Arrangeable M 1  2  3  4  5  More Samsung semiconductor
KS57C2916 The KS57C2916 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core SAM47 Samsung Arrangeable 1  2  3  4  5  More Samsung semiconductor
KS57C3204 The KS57C3204 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core SAM47 Samsung Arrangeable 1  2  3  4  5  More Samsung semiconductor
S3C72I9 The S3C72I9 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core SAM47 Samsung Arrangeable M 1  2  3  4  5  More Samsung semiconductor
KS57C3316 The KS57C3316 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core SAM47 Samsung Arrangeable 1  2  3  4  5  More Samsung semiconductor

Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn