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S3C4510B Datasheet(PDF) 2 Page - Samsung semiconductor |
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S3C4510B Datasheet(HTML) 2 Page - Samsung semiconductor |
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2 / 422 page 
PRODUCT OVERVIEW S3C4510B 1-2 FEATURES Architecture • Integrated system for embedded ethernet applications • Fully 16/32-bit RISC architecture • Little/Big-Endian mode supported basically, the internal architecture is big-endian. So, the little-endian mode only support for external memory. • Efficient and powerful ARM7TDMI core • Cost-effective JTAG-based debug solution • Boundary scan System Manager • 8/16/32-bit external bus support for ROM/SRAM, flash memory, DRAM, and external I/O • One external bus master with bus request/ acknowledge pins • Support for EDO/normal or SDRAM • Programmable access cycle (0-7 wait cycles) • Four-word depth write buffer • Cost-effective memory-to-peripheral DMA interface Unified Instruction/Data Cache • Two-way, set-associative, unified 8K-byte cache • Support for LRU (least recently used) protocol • Cache is configurable as an internal SRAM I 2C Serial Interface • Master mode operation only • Baud rate generator for serial clock generation Ethernet Controller • DMA engine with burst mode • DMA Tx/Rx buffers (256 bytes Tx, 256 bytes Rx) • MAC Tx/Rx FIFO buffers (80 bytes Tx, 16 bytes Rx) • Data alignment logic • Endian translation • 100/10-Mbit per second operation • Full compliance with IEEE standard 802.3 • MII and 7-wire 10-Mbps interface • Station management signaling • On-chip CAM (up to 21 destination addresses) • Full-duplex mode with PAUSE feature • Long/short packet modes • PAD generation HDLCs • HDLC protocol features: — Flag detection and synchronization — Zero insertion and deletion — Idle detection and transmission — FCS generation and detection (16-bit) — Abort detection and transmission • Address search mode (expandable to 4 bytes) • Selectable CRC or No CRC mode • Automatic CRC generator preset • Digital PLL block for clock recovery • Baud rate generator • NRZ/NRZI/FM/Manchester data formats for Tx/Rx • Loop-back and auto-echo modes • Tx/Rx FIFOs have 8-word (8 × 32-bit) depth • Selectable 1-word or 4-word data transfer mode • Data alignment logic • Endian translation • Programmable interrupts • Modem interface • Up to 10 Mbps operation • HDLC frame length based on octets • 2-channel DMA buffer descriptor for Tx/Rx on each HDLC |
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