KM6264B Family

ELECTRONICS

CMOS SRAM

Revision. 0.0

Auust. 1996

9

FUNCTIONAL DESCRIPTION

/CS1

H

X

L

L

L

/WE

X

X

H

H

L

Mode

Power Down

Power Down

Output Disable

Read

Write

Current Mode

Isb, Isb1

Isb, Isb1

Icc

Icc

Icc

I/O Pin

High-Z

High-Z

High-Z

Dout

Din

/OE

X

X

H

L

X

CS2

X

L

H

H

H

Notes(Write Cycle)

1. A write occurs during the overlap of a low /CS1, a high CS2 and a low /WE. A write begins at the latest transition

among /CS1 going low, CS2 going high and /WE going low. A write ends at the earliest transition among /CS1 going

high, CS2 going low and /WE going high, tWP is measured from the beginning of write to the end of write.

2. tCW is measured from the later of /CS1 going low or CS2 going high to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR1 applied in case a write ends at /CS1, or /WE

going high, tWR2 applied in case a write ends at CS2 going to low.

Address

/CS1

/WE

Data in

Data out

Data Vailid

High - Z

High - Z

DH

t

CS2

* X means don't care