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KM62256CLG-7 Datasheet(PDF) 2 Page - Samsung semiconductor |
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KM62256CLG-7 Datasheet(HTML) 2 Page - Samsung semiconductor |
2 / 9 page Revision 4.0 KM62256C Family CMOS SRAM December 1997 2 32Kx8 bit Low Power CMOS Static RAM The KM62256C family is fabricated by SAMSUNG ′s advanced CMOS process technology. The family supports various operat- ing temperature ranges and has various package types for user flexibility of system design. The family also support low data retention voltage for battery back-up operation with low data retention current. GENERAL DESCRIPTION FEATURES • Process Technology : 0.7µm CMOS • Organization : 32Kx8 • Power Supply Voltage : Single 5V±10% • Low Data Retention Voltage : 2V(Min) • Three state output and TTL Compatible • Package Type : 28-DIP-600, 28-SOP-450, 28-TSOP1 -0813.4F/R PIN DESCRIPTION A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS VCC WE A13 A8 A9 A11 OE A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 NameName Function A0~A14 Address Inputs WE Write Enable Input CS Chip Select Input OE Output Enable Input I/O1~I/O8 Data Inputs/Outputs Vcc Power(5V) Vss Ground 28-DIP 28-SOP 15 16 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PRODUCT FAMILY Product Family Operating Temperature. Speed(ns) PKG Type Power Dissipation Standby (ISB1, Max) Operating (Icc2) KM62256CL Commercial (0~70 °C) 55/70ns 28-DIP, 28-SOP 28-TSOP I R/F 100 µA 70mA KM62256CL-L 20 µA KM62256CLE Extended (-25~85 °C) 70ns 28-SOP 28-TSOP I R/F 100 µA KM62256CLE-L 50 µA KM62256CLI Industrial (-40~85 °C) 70ns 28-SOP 28-TSOP I R/F 100 µA KM62256CLI-L 50 µA FUNCTIONAL BLOCK DIAGRAM A11 A9 A8 A13 WE VCC A3 A14 A12 A7 A6 A5 A4 A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 28-TSOP Type I - Forward 1 2 3 4 5 6 7 8 9 10 11 12 13 14 27 26 28 25 24 23 22 21 20 19 18 17 16 15 OE 28-TSOP A11 A9 A8 A13 WE VCC A3 A14 A12 A7 A6 A5 A4 A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 27 26 28 25 24 23 22 21 20 19 18 17 16 15 OE Type I - Reverse SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. Precharge circuit. Memory array 512 rows 64 ×8 columns I/O Circuit Column select Clk gen. Row select A0 A1 A2 A9 A10 A11 A3 A4 A5 A6 A7 A8 A13 CS WE I/O1 Data cont Data cont OE I/O8 A12 A14 Control Logic |
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