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KM48S16030B Datasheet(PDF) 3 Page - Samsung semiconductor

Part No. KM48S16030B
Description  128Mbit SDRAM 4M x 8Bit x 4 Banks Synchronous DRAM LVTTL
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Maker  SAMSUNG [Samsung semiconductor]
Homepage  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

KM48S16030B Datasheet(HTML) 3 Page - Samsung semiconductor

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KM48S16030B
CMOS SDRAM
Rev. 0.1 Jun. 1999
The KM48S16030B is 134,217,728 bits synchronous high data
rate Dynamic RAM organized as 4 x 4,194,304 words by 8 bits,
fabricated with SAMSUNG
′s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance mem-
ory system applications.
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)
GENERAL DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
4M x 8Bit x 4 Banks Synchronous DRAM
Bank Select
Data Input Register
4M x 8
4M x 8
Column Decoder
Latency & Burst Length
Programming Register
LCKE
LRAS
LCBR
LWE
LDQM
CLK
CKE
CS
RAS
CAS
WE
DQM
LWE
LDQM
DQi
CLK
ADD
LCAS
LWCBR
4M x 8
4M x 8
Timing Register
* Samsung Electronics reserves the right to change products or specification without notice.
ORDERING INFORMATION
Part No.
Max Freq.
Interface Package
KM48S16030BT-G/FA
133MHz(CL=3)
LVTTL
54
TSOP(II)
KM48S16030BT-G/F8
125MHz(CL=3)
KM48S16030BT-G/FH
100MHz(CL=2)
KM48S16030BT-G/FL
100MHz(CL=3)
KM48S16030BT-G/F10 66MHz(CL=2 &3)


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