KD16903

DATA PROCESSOR

8

- I

The acknowledge related clock pulse is generated by a microcontroller.

The transmitter releases the SDA line (high) during the acknowledge clock pulse. The receiver must pull down

the SDA line during the acknowledge clock pulse so that it remains stable low during the high period of this clock

pulse. The slave-transmitter generates negative acknowledge when read operation processes. The negative

acknowledge is generated by a master (microcontroller).

SCL

SDA

S

1 0 0 0 0

A0

A

W

A

A P

0

S

1 0 0 0 0 0

0 0

P

LSB

MSB

DATA

LSB

MSB

Function Address

LSB

MSB

Chip Address

SCL

SDA

S

1 0 0 0 0

A0

A

R

A

N/

A

P

0

S

1 0 0 0 0 0

0 1

P

LSB

MSB

DATA

LSB

MSB

Function Address

LSB

MSB

Chip Address

Commands are sent from MSM to KD16903 via the I2C (SDA/SCL) bus, triggered by the input signal CKIN. To

achieve immunity towards noise, the glitch protection circuitry must be put into operation, thereby meeting the

I2C specification.

Thus CKIN should be input with the SDA/SCL.

Another issue is, at least 100 clock(CKIN) cycles are needed to execute the command completely by the

KD16903. Even as the end condition of the I2C interface is met, the MSM must supply KD16903 with CKIN, as