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K9F5608Q0C-HCB0 Datasheet(PDF) 10 Page - Samsung semiconductor |
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K9F5608Q0C-HCB0 Datasheet(HTML) 10 Page - Samsung semiconductor |
10 / 39 page K9F5616U0C-YCB0,YIB0,PCB0,PIB0 FLASH MEMORY 9 K9F5616U0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5616Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-VCB0,VIB0,FCB0,FIB0 PRODUCT INTRODUCTION The K9F56XXX0C is a 264Mbit(276,824,064 bit) memory organized as 65,536 rows(pages) by 528(X8 device) or 264(X16 device) columns. Spare eight columns are located from column address of 512~527(X8 device) or 256~263(X16 device). A 528-byte(X8 device) or 264-word(X16 device) data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations.The memory array is made up of 16 cells that are serially con- nected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of two NAND structures. A NAND structure consists of 16 cells. Total 16896 NAND cells reside in a block. The array organization is shown in Figure 2-1,2-2. The pro- gram and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 2048 separately erasable 16K-Byte(X8 device) or 8K-Word(X16 device) blocks. It indicates that the bit by bit erase oper- ation is prohibited on the K9F56XXX0C. The K9F56XXX0C has addresses multiplexed into 8 I/Os(X16 device case : lower 8 I/Os). K9F5616X0C allows sixteen bit wide data transport into and out of page registers. This scheme dramatically reduces pin counts while providing high performance and allows systems upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O ′s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset command, Read command, Status Read command, etc require just one cycle bus. Some other com- mands like Page Program and Copy-back Program and Block Erase, require two cycles: one cycle for setup and the other cycle for execution. The 32M-byte(X8 device) or 16M-word(X16 device) physical space requires 24 addresses, thereby requiring three cycles for word-level addressing: column address, low row address and high row address, in that order. Page Read and Page Program need the same three address cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9F56XXX0C. The device includes one block sized OTP(One Time Programmable), which can be used to increase system security or to provide identification capabilities. Detailed information can be obtained by contact with Samsung. Table 1. COMMAND SETS NOTE : 1. The 01h command is available only on X8 device(K9F5608X0C). Caution : Any undefined command inputs are prohibited except for above command set of Table 1. Function 1st. Cycle 2nd. Cycle Acceptable Command during Busy Read 1 00h/01h(1) - Read 2 50h - Read ID 90h - Reset FFh - O Page Program 80h 10h Copy-Back Program 00h 8Ah Lock 2Ah - Unlock 23h 24h Lock-tight 2Ch - Read Block Lock Status 7Ah - Block Erase 60h D0h Read Status 70h - O |
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