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K9F5608U0B-VCB0 Datasheet(PDF) 8 Page - Samsung semiconductor |
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K9F5608U0B-VCB0 Datasheet(HTML) 8 Page - Samsung semiconductor |
8 / 34 page FLASH MEMORY 8 K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-VCB0,VIB0,FCB0,FIB0 512Byte 16 Byte Figure 1-1. K9F5608X0B (X8) FUNCTIONAL BLOCK DIAGRAM Figure 2-1. K9F5608X0B (X8) ARRAY ORGANIZATION NOTE : Column Address : Starting Address of the Register. 00h Command(Read) : Defines the starting address of the 1st half of the register. 01h Command(Read) : Defines the starting address of the 2nd half of the register. * A8 is set to "Low" or "High" by the 00h or 01h Command. * The device ignores any additional input of address cycles than reguired. I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 1st Cycle A0 A1 A2 A3 A4 A5 A6 A7 2nd Cycle A9 A10 A11 A12 A13 A14 A15 A16 3rd Cycle A17 A18 A19 A20 A21 A22 A23 A24 VCC X-Buffers 256M + 8M Bit Command NAND Flash ARRAY (512 + 16)Byte x 65536 Y-Gating Page Register & S/A I/O Buffers & Latches Latches & Decoders Y-Buffers Latches & Decoders Register Control Logic & High Voltage Generator Global Buffers Output Driver VSS A9 - A24 A0 - A7 Command CE RE WE WP I/0 0 I/0 7 VCC/VCCQ VSS A8 1st half Page Register (=256 Bytes) 2nd half Page Register (=256 Bytes) 64K Pages (=2,048 Blocks) 512 Byte 8 bit 16 Byte 1 Block =32 Pages = (16K + 512) Byte I/O 0 ~ I/O 7 1 Page = 528 Byte 1 Block = 528 Byte x 32 Pages = (16K + 512) Byte 1 Device = 528Bytes x 32Pages x 2048 Blocks = 264 Mbits Column Address Row Address (Page Address) Page Register CLE ALE |
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