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K9F1208Q0A Datasheet(PDF) 31 Page - Samsung semiconductor |
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K9F1208Q0A Datasheet(HTML) 31 Page - Samsung semiconductor |
31 / 39 page K9F5616U0C-YCB0,YIB0,PCB0,PIB0 FLASH MEMORY 30 K9F5616U0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5616Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-VCB0,VIB0,FCB0,FIB0 Figure 12. Block Erase Operation BLOCK ERASE The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup com- mand(60h). Only address A14 to A24 is valid while A9 to A13 is ignored. The Erase Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 12 details the sequence. 60h Block Add. : A9 ~ A24 R/B Address Input(2Cycle) I/O0 Pass D0h 70h Fail tBERS READ STATUS The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to table 4 for specific Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, a read command(00h or 50h) should be given before sequential page read cycle. Table4. Read Status Register Definition I/O # Status Definition I/O 0 Program / Erase "0" : Successful Program / Erase "1" : Error in Program / Erase I/O 1 Reserved for Future Use "0" I/O 2 "0" I/O 3 "0" I/O 4 "0" I/O 5 "0" I/O 6 Device Operation "0" : Busy "1" : Ready I/O 7 Write Protect "0" : Protected "1" : Not Protected I/O 8~15 Not use Don’t care I/Ox |
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