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K9F1208Q0A Datasheet(PDF) 12 Page - Samsung semiconductor |
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K9F1208Q0A Datasheet(HTML) 12 Page - Samsung semiconductor |
12 / 39 page K9F5616U0C-YCB0,YIB0,PCB0,PIB0 FLASH MEMORY 11 K9F5616U0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5616Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-VCB0,VIB0,FCB0,FIB0 CAPACITANCE(TA=25 °C, VCC=1.8V/3.3V, f=1.0MHz) NOTE : Capacitance is periodically sampled and not 100% tested. Item Symbol Test Condition Min Max Unit Input/Output Capacitance CI/O VIL=0V - 10 pF Input Capacitance CIN VIN=0V - 10 pF VALID BLOCK NOTE : 1. The K9F56XXX0C may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits . Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks. 2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction. 3. Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space. Parameter Symbol Min Typ. Max Unit Valid Block Number NVB 2013 - 2048 Blocks Program/Erase Characteristics Parameter Symbol Min Typ Max Unit Program Time tPROG - 200 500 µs Dummy Busy Time for the Lock or Lock-tight Block tLBSY - 5 10 µs Number of Partial Program Cycles in the Same Page Main Array Nop - - 2 cycles Spare Array - - 3 cycles Block Erase Time tBERS - 2 3 ms AC TEST CONDITION (K9F56XXX0C-XCB0 :TA=0 to 70 °C, K9F56XXX0C-XIB0:TA=-40 to 85°C K9F56XXQ0C : Vcc=1.70V~1.95V , K9F56XXU0C : Vcc=2.7V~3.6V unless otherwise noted) Parameter K9F56XXQ0C K9F56XXU0C Input Pulse Levels 0V to VccQ 0.4V to 2.4V Input Rise and Fall Times 5ns 5ns Input and Output Timing Levels VccQ/2 1.5V K9F56XXQ0C:Output Load (VccQ:1.8V +/-10%) K9F56XXU0C:Output Load (VccQ:3.0V +/-10%) 1 TTL GATE and CL=30pF 1 TTL GATE and CL=50pF K9F56XXU0C:Output Load (VccQ:3.3V +/-10%) - 1 TTL GATE and CL=100pF MODE SELECTION NOTE : 1. X can be VIL or VIH. 2. WP should be biased to CMOS high or CMOS low for standby. CLE ALE CE WE RE PRE WP Mode H L L H X X Read Mode Command Input L H L H X X Address Input(3clock) H L L H X H Write Mode Command Input L H L H X H Address Input(3clock) L L L H X H Data Input L L L H X X Data Output X X X X H X X During Read(Busy) on K9F5608U0C_Y,P or K9F5608U0C_V,F L L L H H X X During Read(Busy) on the devices except K9F5608U0C_Y,P and K9F5608U0C_V,F X X X X X X H During Program(Busy) X X X X X X H During Erase(Busy) X X(1) X X X X L Write Protect X X H X X 0V/VCC(2) 0V/VCC(2) Stand-by |
Similar Part No. - K9F1208Q0A |
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Similar Description - K9F1208Q0A |
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