K6R1008C1A-C, K6R1008C1A-I

CMOS SRAM

PRELIMINARY

Rev 4.0

- 2 -

February 1998

128K x 8 Bit High-Speed CMOS Static RAM

GENERAL DESCRIPTION

FEATURES

• Fast Access Time 12, 15, 20ns(Max.)

• Low Power Dissipation

Standby (TTL)

: 25mA(Max.)

(CMOS) : 8mA(Max.)

Operating K6R1008C1A-12 : 170mA(Max.)

K6R1008C1A-15 : 165mA(Max.)

K6R1008C1A-20 : 160mA(Max.)

• Single 5.0V

±10% Power Supply

• TTL Compatible Inputs and Outputs

• I/O Compatible with 3.3V Device

• Fully Static Operation

- No Clock or Refresh required

• Three State Outputs

• Center Power/Ground Pin Configuration

• Standard Pin Configuration

K6R1008C1A-J : 32-SOJ-400

K6R1008C1A-T: 32-TSOP2-400CF

K6R1008C1A-C12/C15/C20

Commercial Temp.

K6R1008C1A-I12/I15/I20

Industrial Temp.

ORDERING INFORMATION

Clk Gen.

CS

WE

OE

FUNCTIONAL BLOCK DIAGRAM

Data

Cont.

Column Select

CLK

Gen.

Pre-Charge Circuit

Memory Array

512 Rows

256x8 Columns

I/O Circuit

PIN FUNCTION

Pin Name

Pin Function

Address Inputs

WE

Write Enable

CS

Chip Select

OE

Output Enable

Data Inputs/Outputs

Power(+5.0V)

Ground

The K6R1008C1A is a 1,048,576-bit high-speed Static Random

Access Memory organized as 131,072 words by 8 bits. The

K6R1008C1A uses 8 common input and output lines and has

an output enable pin which operates faster than address access

time at read cycle. The device is fabricated using SAMSUNG

′s

advanced CMOS process and designed for high-speed circuit

technology. It is particularly well suited for use in high-density

high-speed system applications. The K6R1008C1A is packaged

in a 400mil 32-pin plastic SOJ or TSOP2 forward.

SOJ/

TSOP2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

OE

Vss

Vcc

CS

Vcc

Vss

WE