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K4S281632M Datasheet(PDF) 2 Page - Samsung semiconductor

Part No. K4S281632M
Description  128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
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Manufacturer  SAMSUNG [Samsung semiconductor]
Direct Link  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

K4S281632M Datasheet(HTML) 2 Page - Samsung semiconductor

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K4S281632M
CMOS SDRAM
Rev. 0.0 Aug. 1999
The K4S281632M is 134,217,728 bits synchronous high data
rate Dynamic RAM organized as 4 x 2,097,152 words by 16
bits, fabricated with SAMSUNG
′s high performance CMOS
technology. Synchronous design allows precise cycle control
with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programma-
ble burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)
GENERAL DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
2M x 16Bit x 4 Banks Synchronous DRAM
ORDERING INFORMATION
Part No.
Max Freq.
Inter-
Package
K4S281632M-TC/L80
125MHz(CL=3)
LVTTL
54pin
TSOP(II)
K4S281632M-TC/L1H
100MHz(CL=2)
K4S281632M-TC/L1L
100MHz(CL=3)
K4S281632M-TC/L10 66MHz(CL=2 &3)
Bank Select
Data Input Register
2M x 16
2M x 16
Column Decoder
Latency & Burst Length
Programming Register
LCKE
LRAS
LCBR
LWE
LDQM
CLK
CKE
CS
RAS
CAS
WE
LDQM
LWE
LDQM
DQi
CLK
ADD
LCAS
LWCBR
2M x 16
2M x 16
Timing Register
UDQM
* Samsung Electronics reserves the right to change products or specification without notice.


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