Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

K4S281632D Datasheet(PDF) 3 Page - Samsung semiconductor

Part No. K4S281632D
Description  128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
Download  11 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  SAMSUNG [Samsung semiconductor]
Homepage  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

K4S281632D Datasheet(HTML) 3 Page - Samsung semiconductor

  K4S281632D Datasheet HTML 1Page - Samsung semiconductor K4S281632D Datasheet HTML 2Page - Samsung semiconductor K4S281632D Datasheet HTML 3Page - Samsung semiconductor K4S281632D Datasheet HTML 4Page - Samsung semiconductor K4S281632D Datasheet HTML 5Page - Samsung semiconductor K4S281632D Datasheet HTML 6Page - Samsung semiconductor K4S281632D Datasheet HTML 7Page - Samsung semiconductor K4S281632D Datasheet HTML 8Page - Samsung semiconductor K4S281632D Datasheet HTML 9Page - Samsung semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 3 / 11 page
background image
CMOS SDRAM
K4S281632D
Rev. 0.1 Sept. 2001
The K4S281632D is 134,217,728 bits synchronous high data
rate Dynamic RAM organized as 4 x 2,097,152 words by 16
bits, fabricated with SAMSUNG
′s high performance CMOS
technology. Synchronous design allows precise cycle control
with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programma-
ble burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)
GENERAL DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
2M x 16Bit x 4 Banks Synchronous DRAM
Bank Select
Data Input Register
2M x 16
2M x 16
Column Decoder
Latency & Burst Length
Programming Register
LCKE
LRAS
LCBR
LWE
LDQM
CLK
CKE
CS
RAS
CAS
WE
LDQM
LWE
LDQM
DQi
CLK
ADD
LCAS
LWCBR
2M x 16
2M x 16
Timing Register
UDQM
* Samsung Electronics reserves the right to change products or specification without notice.
ORDERING INFORMATION
Part No.
Max Freq.
Interface Package
K4S281632D-TC/L55
183MHz(CL=3)
LVTTL
54
TSOP(II)
K4S281632D-TC/L60
166MHz(CL=3)
K4S281632D-TC/L7C
133MHz(CL=2)
K4S281632D-TC/L75
133MHz(CL=3)
K4S281632D-TC/L1H
100MHz(CL=2)
K4S281632D-TC/L1L
100MHz(CL=3)


Html Pages

1  2  3  4  5  6  7  8  9  10  11 


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn