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K4S280432A Datasheet(PDF) 2 Page - Samsung semiconductor

Part No. K4S280432A
Description  128Mbit SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM LVTTL
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Maker  SAMSUNG [Samsung semiconductor]
Homepage  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

K4S280432A Datasheet(HTML) 2 Page - Samsung semiconductor

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K4S280432A
CMOS SDRAM
Rev. 0.0 Aug. 1999
The
K4S280432A is 134,217,728 bits synchronous high data
rate Dynamic RAM organized as 4 x 8,388,608 words by 4 bits,
fabricated with SAMSUNG
′s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance mem-
ory system applications.
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 Page )
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (4K Cycle)
GENERAL DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
8M x 4Bit x 4 Banks Synchronous DRAM
Bank Select
Data Input Register
8M x 4
8M x 4
Column Decoder
Latency & Burst Length
Programming Register
LCKE
LRAS
LCBR
LWE
LDQM
CLK
CKE
CS
RAS
CAS
WE
DQM
LWE
LDQM
DQi
CLK
ADD
LCAS
LWCBR
8M x 4
8M x 4
Timing Register
* Samsung Electronics reserves the right to change products or specification without notice.
ORDERING INFORMATION
Part No.
Max Freq.
Interface Package
K4S280432A-TC/L75
133MHz(CL=3)
LVTTL
54
TSOP(II)
K4S280432A-TC/L80
125MHz(CL=3)
K4S280432A-TC/L1H
100MHz(CL=2)
K4S280432A-TC/L1L
100MHz(CL=3)
K4S280432A-TC/L10
66MHz(CL=2 &3)


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