K4F160811D datasheet(8/20 Pages) SAMSUNG

Part #	K4F160811D

Description	2M x 8Bit CMOS Dynamic RAM with Fast Page Mode

Download	20 Pages

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Manufacturer	SAMSUNG [Samsung semiconductor]

Direct Link	http://www.samsung.com/Products/Semiconductor

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K4F170811D, K4F160811D

CMOS DRAM

K4F170812D, K4F160812D

NOTES

An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles

before proper device operation is achieved.

VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between

VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.

Measured with a load equivalent to 2 TTL(5V)/1 TTL(3.3V) loads and 100pF.

Operation within the

tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only.

If

tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.

Assumes that

tRCD

≥tRCD(max).

tOFF(min)and tOEZ(max) define the time at which the output achieves the open circuit condition and are not referenced Voh or

Vol.

tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electrical charac-

teristics only. If

tWCS

≥tWCS(min), the cycle is an early write cycle and the data output will remain high impedance for the dura-

tion of the cycle. If

tCWD

≥tCWD(min), tRWD≥tRWD(min) and tAWD≥tAWD(min), then the cycle is a read-modify-write cycle and the

data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition

of the data out is indeterminate.

Either

tRCH or tRRH must be satisfied for a read cycle.

These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in read-modify-write cycles.

Operation within the

tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only.

If

tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.

These specifications are applied in the test mode.

In test mode read cycle, the value of

tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters

should be specified in test mode cycles by adding the above value to the specified value in this data sheet.

If

tRASS

≥100us, then RAS precharge time must use tRPS instead of tRP.

For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K)/2048(2K) cycles of burst refresh must be exe-

cuted within 64ms/32ms before and after self refresh, in order to meet refresh specification.

For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should be executed with in 15.6us immedi-

ately before and after self refresh in order to meet refresh specification.

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