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K4E661612C Datasheet(PDF) 9 Page - Samsung semiconductor

Part # K4E661612C
Description  4M x 16bit CMOS Dynamic RAM with Extended Data Out
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Manufacturer  SAMSUNG [Samsung semiconductor]
Direct Link  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

K4E661612C Datasheet(HTML) 9 Page - Samsung semiconductor

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CMOS DRAM
K4E661612C,K4E641612C
tCWL is specified from W falling edge to the earlier CAS rising edge.
tCSR is referenced to earlier CAS falling before RAS transition low.
tCHR is referenced to the later CAS rising high after RAS transition low.
tDS is specified for the earlier CAS falling edge and tDH is specified by the later CAS falling edge in early write cycle.
If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going.
tASC
≥6ns, Assume tT=2.0ns, if tASC≤6ns, then tHPC(min) and tCAS(min) must be increased by the value of "6ns-tASC".
If
tRASS
≥100us, then RAS precharge time must use tRPS instead of tRP.
For RAS-only-Refresh and Burst CAS-before-RAS refresh mode, 4096 cycles(4K/8K) of burst refresh must be executed within
64ms before and after self refresh, in order to meet refresh specification.
For distributed CAS-before-RAS with 15.6us interval, CBR refresh should be executed with in 15.6us immediately before and
after self refresh in order to meet refresh specification.
tCSR
tCHR
RAS
LCAS
UCAS
tDS
tDH
LCAS
UCAS
DQ0 ~ DQ15
Din
22.
21.
20.
19.
18.
17.
16.
23.
24.


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